Datasheet > 24LC1026TI/SM

24LC1026TI/SM

更新时间： 2022-02-26 09:38:38

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
30页	464K
描述
1024K I2Cï¿½ï¿½ Serial EEPROM

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24LC1026TI/SM 数据手册

24AA1026/24LC1026/24FC1026

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

Name

PIN FUNCTION TABLE

PDIP

SOIC

SOIJ

Function

Not Connected

User Configurable Chip Select

Ground

VSS

SDA

SCL

VCC

Serial Data

Serial Clock

Write-Protect Input

+1.7 to 5.5V (24AA1026)

+2.5 to 5.5V (24LC1026)

+1.8 to 5.5V (24FC1026)

2.1

A1, A2 Chip Address Inputs

3.0

FUNCTIONAL DESCRIPTION

The A1 and A2 inputs are used by the 24XX1026 for

multiple device operations. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the comparison is true.

The 24XX1026 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device

receiving data as a receiver. The bus must be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24XX1026 works as a slave. Both master and slave

can operate as a transmitter or receiver, but the master

device determines which mode is activated.

Up to four devices may be connected to the same bus

by using different Chip Select bit combinations. In most

applications, the chip address inputs A1 and A2 are

hard-wired to logic ‘0’ or logic ‘1’. For applications in

which these pins are controlled by a microcontroller or

other programmable device, the chip address pins

must be driven to logic ‘0’ or logic ‘1’ before normal

device operation can proceed.

2.2

Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an

open-drain terminal, therefore, the SDA bus requires a

pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k

for 400 kHz and 1 MHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.3

Serial Clock (SCL)

This input is used to synchronize the data transfer from

and to the device.

2.4

Write-Protect (WP)

This pin must be connected to either VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited, but read operations are

not affected.

DS20002270E-page 6

 2011-2015 Microchip Technology Inc.

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