25AA640/25LC640/25C640
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 3-2.
3.5
Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The Write Protect Enable (WPEN) bit is a non-volatile
bit that is available as an enable bit for the WP pin.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the status register control the
programmable hardware write protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write protected,
only writes to non-volatile bits in the status register are
disabled. See Table 3-3 for a matrix of functionality on
the WPEN bit.
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1 BP0 WEL WIP
The Write-In-Process (WIP) bit indicates whether the
25xx640 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register.The state of this bit can always be updated via
the WREN or WRDI commands regardless of the state
of write protection on the status register. This bit is
read only.
See Figure 3-7 for WRSR timing sequence
TABLE 3-2:
BP1
ARRAY PROTECTION
Array Addresses
BP0
Write Protected
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
0
0
0
1
none
upper 1/4
(1800h - 1FFFh)
upper 1/2
(1000h - 1FFFh)
See Figure 3-6 for RDSR timing sequence
1
1
0
1
3.6
Write Status Register(WRSR)
all
(0000h - 1FFFh)
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
FIGURE 3-6: READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
instruction
0
0
0
0
0
1
0
1
data from status register
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
data to status register
SCK
SI
instruction
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
high impedance
SO
1997 Microchip Technology Inc.
Preliminary
DS21223A-page 9
5秒后页面跳转
SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
AT89C51单片机资料手册详细解析及应用示例
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
