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24C16B-ESL

更新时间： 2024-01-16 17:18:55

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	78K
描述
8K/16K 5.0V I 2 C O Serial EEPROMs

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24C16B-ESL 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.65
数据保留时间-最小值：	10	耐久性：	10000 Write/Erase Cycles
I2C控制字节：	1010MMMR	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0	内存密度：	16384 bit
内存集成电路类型：	EEPROM	内存宽度：	8
端子数量：	8	字数：	2048 words
字数代码：	2000	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
电源：	5 V	认证状态：	Not Qualified
串行总线类型：	I2C	最大待机电流：	0.0001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
写保护：	HARDWARE	Base Number Matches：	1

24C16B-ESL 数据手册

24C08B/16B

3.6

Device Addressing

4.0

WRITE OPERATION

A control byte is the ﬁrst byte received following the

start condition from the master device. The control byte

consists of a 4-bit control code, for the 24C08B/16B this

is set as 1010 binary for read and write operations. The

next three bits of the control byte are the block select

bits (B2, B1, B0). They are used by the master device

to select which of the eight 256 word blocks of memory

are to be accessed. These bits are in effect the three

most signiﬁcant bits of the word address.

4.1

Byte Write

Following the start condition from the master, the

device code (4 bits), the block address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore the next byte transmitted by

the master is the word address and will be written into

the address pointer of the 24C08B/16B. After receiving

another acknowledge signal from the 24C08B/16B the

master device will transmit the data word to be written

into the addressed memory location. The 24C08B/16B

acknowledges again and the master generates a stop

condition. This initiates the internal write cycle, and dur-

ing this time the 24C08B/16B will not generate

acknowledge signals (Figure 4-1).

The last bit of the control byte deﬁnes the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the 24C08B/16B monitors

the SDA bus checking the device type identiﬁer being

transmitted, upon a 1010 code the slave device outputs

an acknowledge signal on the SDA line. Depending on

the state of the R/W bit, the 24C08B/16B will select a

read or write operation.

4.2

Page Write

Control

Code

Operation

Block Select

R/W

The write control byte, word address and the ﬁrst data

byte are transmitted to the 24C08B/16B in the same

way as in a byte write. But instead of generating a stop

condition the master transmits up to 16 data bytes to

the 24C08B/16B which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the four lower order address

pointer bits are internally incremented by one. The

higher order seven bits of the word address remains

constant. If the master should transmit more than 16

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

Read

Write

1010

Block Address

FIGURE 3-2: CONTROL BYTE

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W

FIGURE 4-1: BYTE WRITE

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS

DATA

SDA LINE

BUS ACTIVITY

FIGURE 4-2: PAGE WRITE

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 1

DATA n + 15

SDA LINE

BUS ACTIVITY

1996 Microchip Technology Inc.

DS21081D-page 5

1 2 3 456 7 8...12

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