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24C16B-ESL

更新时间： 2024-01-09 20:35:36

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	78K
描述
8K/16K 5.0V I 2 C O Serial EEPROMs

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24C16B-ESL 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.65
数据保留时间-最小值：	10	耐久性：	10000 Write/Erase Cycles
I2C控制字节：	1010MMMR	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0	内存密度：	16384 bit
内存集成电路类型：	EEPROM	内存宽度：	8
端子数量：	8	字数：	2048 words
字数代码：	2000	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
电源：	5 V	认证状态：	Not Qualified
串行总线类型：	I2C	最大待机电流：	0.0001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
写保护：	HARDWARE	Base Number Matches：	1

24C16B-ESL 数据手册

24C08B/16B

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The 24C08B/16B supports a Bi-directional 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is deﬁned as transmitter, and a device

receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock

(SCL), controls the bus access, and generates the

START and STOP conditions, while the 24C08B/16B

works as slave. Both, master and slave can operate as

transmitter or receiver but the master device deter-

mines which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwrite does occur it will replace data in a ﬁrst in ﬁrst

out fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

Note: The 24C08B/16B does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by NOT generating an acknowledge

bit on the last byte that has been clocked out of the

slave. In this case, the slave (24C08B/16B) will leave

the data line HIGH to enable the master to generate the

STOP condition.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

DS21081D-page 4

1996 Microchip Technology Inc.

1 2 345 6 7...12

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