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24AA02E48-IOT

更新时间： 2024-01-31 05:16:58
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
28页 494K
描述
2K I2C™ Serial EEPROMs with EUI-48™ Node Identity

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24AA02E48-IOT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：5 weeks
风险等级：1.22Is Samacsys：N
最大时钟频率 (fCLK)：0.4 MHz数据保留时间-最小值：200
耐久性：1000000 Write/Erase CyclesI2C控制字节：1010XXXR
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm内存密度：1024 bit
内存集成电路类型：EEPROM内存宽度：8
湿度敏感等级：3功能数量：1
端子数量：8字数：128 words
字数代码：128工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128X8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：SERIAL峰值回流温度（摄氏度）：260
电源：1.8/5 V认证状态：Not Qualified
座面最大高度：1.75 mm串行总线类型：I2C
最大待机电流：0.000001 A子类别：EEPROMs
最大压摆率：0.003 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mm最长写入周期时间 (tWC)：5 ms
Base Number Matches：1

24AA02E48-IOT 数据手册

 浏览型号24AA02E48-IOT的Datasheet PDF文件第6页浏览型号24AA02E48-IOT的Datasheet PDF文件第7页浏览型号24AA02E48-IOT的Datasheet PDF文件第8页浏览型号24AA02E48-IOT的Datasheet PDF文件第10页浏览型号24AA02E48-IOT的Datasheet PDF文件第11页浏览型号24AA02E48-IOT的Datasheet PDF文件第12页 
24AA02E48/24AA025E48  
If the master should transmit more than 8 words (16 for  
the 24AA025E48) prior to generating the Stop condi-  
tion, the address counter will roll over and the previously  
received data will be overwritten. As with the byte write  
operation, once the Stop condition is received an inter-  
nal write cycle will begin (Figure 6-2).  
6.0  
6.1  
WRITE OPERATION  
Byte Write  
Following the Start condition from the master, the  
device code (4 bits), the chip address (3 bits) and the  
R/W bit which is a logic-low, is placed onto the bus by  
the master transmitter. This indicates to the addressed  
slave receiver that a byte with a word address will fol-  
low once it has generated an Acknowledge bit during  
the ninth clock cycle. Therefore, the next byte transmit-  
ted by the master is the word address and will be writ-  
ten into the Address Pointer of the 24AAXXXE48. After  
receiving another Acknowledge signal from the  
24AAXXXE48, the master device will transmit the data  
word to be written into the addressed memory location.  
The 24AAXXXE48 acknowledges again and the mas-  
ter generates a Stop condition. This initiates the inter-  
nal write cycle and, during this time, the 24AAXXXE48  
will not generate Acknowledge signals (Figure 6-1).  
Note:  
Page write operations are limited to writing  
bytes within single physical page  
a
regardless of the number of bytes  
actually being written. Physical page  
boundaries start at addresses that are  
integer multiples of the page buffer size (or  
‘page size’) and end at addresses that are  
integer multiples of [page size – 1]. If a  
page write command attempts to write  
across a physical page boundary, the  
result is that the data wraps around to the  
beginning of the current page (overwriting  
data previously stored there), instead of  
being written to the next page, as might be  
expected. It is therefore necessary for the  
application software to prevent page write  
operations that would attempt to cross a  
page boundary.  
6.2  
Page Write  
The write-control byte, word address and the first data  
byte are transmitted to the 24AAXXXE48 in the same  
way as in a byte write. However, instead of generating  
a Stop condition, the master transmits up to 8 data bytes  
to the 24AAXXXE48, which are temporarily stored in the  
on-chip page buffer and will be written into memory  
once the master has transmitted a Stop condition. Upon  
receipt of each word, the three lower-order Address  
Pointer bits (four for the 24AA025E48) are internally  
incremented by ‘1’. The higher-order five bits (four for  
the 24AA025E48) of the word address remain constant.  
6.3  
Write Protection  
The upper half of the array (80h-FFh) is permanently  
write-protected. Write operations to this address range  
are inhibited. Read operations are not affected.  
The remaining half of the array (00h-7Fh) can be  
written to and read from normally.  
FIGURE 6-1:  
BYTE WRITE  
S
T
A
R
T
S
Bus Activity  
Master  
Control  
Byte  
Word  
Address  
T
O
P
Data  
0
0
SDA Line  
A2*A1*A0*  
1
0
1
S
P
A
C
K
A
C
K
A
C
K
Bus Activity  
Chip  
Select  
Bits  
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.  
FIGURE 6-2:  
PAGE WRITE  
S
S
T
O
P
T
Bus Activity  
Master  
Control  
Byte  
Word  
Address (n)  
A
Data (n)  
Data (n + 1)  
Data (n + 7)  
R
T
*
*
*
1 0 1 0A2 A0 0  
A1  
SDA Line  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity  
Chip  
Select  
Bits  
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.  
2010 Microchip Technology Inc.  
DS22124D-page 9  
1...6789101112...28

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