5秒后页面跳转
捷配首页

Datasheet > 存储 > EEPROM> 24AA024IP
24AA024IP PDF预览

24AA024IP

更新时间： 2024-01-15 17:01:26
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
26页 387K
描述
2K I2C Serial EEPROM

阅读下载

获取价格

24AA024IP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.43
最大时钟频率 (fCLK)：0.4 MHz数据保留时间-最小值：200
耐久性：1000000 Write/Erase CyclesI2C控制字节：1010DDDR
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.4 mm内存密度：2048 bit
内存集成电路类型：EEPROM内存宽度：8
湿度敏感等级：1功能数量：1
端子数量：8字数：256 words
字数代码：256工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256X8封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：SERIAL峰值回流温度（摄氏度）：260
电源：2/5 V认证状态：Not Qualified
座面最大高度：1.2 mm串行总线类型：I2C
最大待机电流：0.000001 A子类别：EEPROMs
最大压摆率：0.003 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3 mm最长写入周期时间 (tWC)：5 ms
写保护：HARDWAREBase Number Matches：1

24AA024IP 数据手册

 浏览型号24AA024IP的Datasheet PDF文件第3页浏览型号24AA024IP的Datasheet PDF文件第4页浏览型号24AA024IP的Datasheet PDF文件第5页浏览型号24AA024IP的Datasheet PDF文件第7页浏览型号24AA024IP的Datasheet PDF文件第8页浏览型号24AA024IP的Datasheet PDF文件第9页 
24AA024/24LC024/24AA025/24LC025  
The data on the line must be changed during the low  
period of the clock signal. There is one bit of data per  
clock pulse.  
4.0  
BUS CHARACTERISTICS  
The following bus protocol has been defined:  
• Data transfer may be initiated only when the bus  
is not busy.  
Each data transfer is initiated with a Start condition and  
terminated with a Stop condition. The number of the  
data bytes transferred between the Start and Stop  
conditions is determined by the master device and is,  
theoretically, unlimited, (though only the last sixteen will  
be stored when performing a write operation). When an  
overwrite does occur, it will replace data in a first-in  
first-out fashion.  
• During data transfer, the data line must remain  
stable whenever the clock line is high. Changes in  
the data line while the clock line is high will be  
interpreted as a Start or Stop condition.  
Accordingly, the following bus conditions have been  
defined (Figure 4-1).  
4.5  
Acknowledge  
4.1  
Bus Not Busy (A)  
Each receiving device, when addressed, is required to  
generate an acknowledge after the reception of each  
byte. The master device must generate an extra clock  
pulse which is associated with this Acknowledge bit.  
Both data and clock lines remain high.  
4.2  
Start Data Transfer (B)  
A high-to-low transition of the SDA line while the clock  
(SCL) is high determines a Start condition. All  
commands must be preceded by a Start condition.  
Note:  
The 24AA024/24LC024/24AA025/24LC025  
does not generate any Acknowledge bits if  
an internal programming cycle is in  
progress.  
4.3  
Stop Data Transfer (C)  
The device that acknowledges has to pull down the SDA  
line during the acknowledge clock pulse in such a way  
that the SDA line is stable low during the high period of  
the acknowledge-related clock pulse. Of course, setup  
and hold times must be taken into account. A master  
must signal an end of data to the slave by not generating  
an Acknowledge bit on the last byte that has been  
clocked out of the slave. In this case, the slave must  
leave the data line high to enable the master to generate  
the Stop condition (Figure 4-2).  
A low-to-high transition of the SDA line while the clock  
(SCL) is high determines a Stop condition. All  
operations must be ended with a Stop condition.  
4.4  
Data Valid (D)  
The state of the data line represents valid data when,  
after a Start condition, the data line is stable for the  
duration of the high period of the clock signal.  
FIGURE 4-1:  
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS  
(A)  
(B)  
(C)  
(D)  
(C) (A)  
SCL  
SDA  
Start  
Condition  
Stop  
Condition  
Address or  
Acknowledge  
Valid  
Data  
Allowed  
to Change  
FIGURE 4-2:  
ACKNOWLEDGE TIMING  
Acknowledge  
Bit  
1
2
3
4
5
6
7
8
9
1
2
3
SCL  
SDA  
Data from transmitter  
Data from transmitter  
Transmitter must release the SDA line at this point allowing  
the Receiver to pull the SDA line low to acknowledge the  
previous eight bits of data.  
Receiver must release the SDA line at this  
point so the Transmitter can continue  
sending data.  
DS21210K-page 6  
© 2007 Microchip Technology Inc.  
1...3456789...26

下载PDF

与24AA024IP相关器件

型号 品牌 描述 获取价格 数据表
24AA024ISN MICROCHIP 2K I2C Serial EEPROM

获取价格
24AA024IST MICROCHIP 2K I2C Serial EEPROM

获取价格
24AA024T-I/MC MICROCHIP 2K I2C⑩ Serial EEPROM

获取价格
24AA024T-I/MCG MICROCHIP 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 2 X 3 MM, 0.90 MM HEIGHT, LEAD FREE, PLASTIC, MO-

获取价格
24AA024T-I/MS MICROCHIP 2K I2C⑩ Serial EEPROM

获取价格
24AA024T-I/MSG MICROCHIP 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LEAD FREE, PLASTIC, MO-187, MSOP-8

获取价格

与24AA024IP相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证