Datasheet > 23S08T-5DCG8

23S08T-5DCG8

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
6页	59K
描述
Clock Driver

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数据手册

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23S08T-5DCG8 数据手册

IDT23S08T

2.5VZERODELAYCLOCKMULTIPLIER

COMMERCIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICS

Symbol

VIL

Parameter

Conditions

Min.

—

1.7

—

Typ.⁽¹⁾

—

Max.

0.7

—

Unit

InputLOWVoltageLevel

Input HIGH Voltage Level

InputLOWCurrent

Input HIGH Current

OutputLOWVoltage

OutputHIGHVoltage

Power Down Current

VIH

—

IIL

VIN = 0V

—

µ A

IIH

VIN = VDD

IOL = 8mA

IOH = -8mA

—

100

0.3

—

VOL

VOH

IDD_PD

—

REF = 0MHz (S2 = S1 = H)

—

µ A

100MHz CLKA

66MHz CLKA

—

IDD

SupplyCurrent

UnloadedOutputs

—

Select Inputs at VDD or GND 33MHz CLKA

—

SWITCHINGCHARACTERISTICS

Symbol Parameter

Conditions

Min.

Typ.

—

Max.

133.3

Unit

OutputFrequency

15pFLoad

MHz

Duty Cycle = t2 ÷ t1

Measured at VDD/2, FOUT = 66.66MHz, 15pF Load

Measuredbetween0.7Vand1.7V,15pFLoad

Alloutputsequallyloaded

RiseTime

—

2.5

FallTime

—

2.5

OutputtoOutputSkewonsame Bank

(-1, -2, -3, -4, -5)

—

200

Output Bank A to Output Bank B (-1, -4, -5)

Output Bank A to Output Bank B Skew (-2, -3)

Alloutputsequallyloaded

—

200

400

Delay, REF Rising Edge to FBK Rising Edge

Device to Device Skew

MeasuredatVDD/2

—

±350

700

200

400

Measured at VDD/2 on the FBK pins of devices

Measuredat66.67MHz,loadedoutputs,15pFLoad

Measuredat133.3MHz,loadedoutputs,15pFLoad

Measuredat66.67MHz,loadedoutputs,15pFLoad

Stable Power Supply, valid clocks presented

on REF and FBK pins

Cycle to Cycle Jitter (-1, -4, -5)

—

Cycle to Cycle Jitter (-2, -3)

PLLLockTime

tLOCK

1 2 345 6

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