Datasheet > 23S09

23S09

更新时间： 2024-11-21 14:58:27

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
9页	473K
描述
3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible

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23S09 数据手册

IDT23S09

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT23S09

3.3V ZERO DELAY

CLOCK BUFFER, SPREAD

SPECTRUM COMPATIBLE

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer,

designedtoaddresshigh-speedclockdistributionapplications. Thezero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• IDT23S09-1 for Standard Drive

• IDT23S09-1H for High Drive

The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09

acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.

The-1Hversionofthisdeviceoperatesupto133MHzfrequencyandhas

higher drive than the -1 device. All parts have on-chip PLLs which lock

to an input clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad. In the absence of an input clock, the

IDT23S09enterspowerdown. Inthismode,thedevicewilldrawlessthan

• No external RC network required

• Operates at 3.3V VDD

• Spread spectrum compatible

• Available in SOIC and TSSOP packages

12µAforCommercialTemperaturerangeandlessthan25µAforIndustrial

temperature range, and the outputs are tri-stated.

The IDT23S09 is characterized for both Industrial and Commercial

operation.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLKA1

PLL

REF

CLKA2

CLKA3

CLKA4

Control

Logic

CLKB1

CLKB2

CLKB3

CLKB4

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

May 9, 2023

12 3 4 5 6 7...9

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