Datasheet > 2308A-3DC8

2308A-3DC8

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
10页	69K
描述
Clock Driver, PDSO16

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数据手册

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2308A-3DC8 数据手册

IDT2308A

3.3VZERODELAYCLOCKMULTIPLIER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

PINCONFIGURATION

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

Rating

Max.

–0.5to+4.6

–0.5to+5.5

–0.5to

Unit

VDD

SupplyVoltageRange

InputVoltageRange(REF)

InputVoltageRange

(except REF)

(2)

REF

FBK

CLKA1

CLKA4

CLKA3

VDD

VDD+0.5

–50

IIK (VI < 0)

InputClampCurrent

ContinuousOutputCurrent

CLKA2

±50

VDD

(VO = 0 to VDD)

VDD or GND

TA = 55°C

(instillair)⁽³⁾

TSTG

GND

CLKB1

CLKB2

GND

CLKB4

CLKB3

ContinuousCurrent

±100

0.7

MaximumPowerDissipation

StorageTemperatureRange

CommercialTemperature

Range

–65to+150

0 to +70

°C

Operating

Temperature

Operating

Temperature

NOTES:

IndustrialTemperature

Range

-40to+85

°C

SOIC/ TSSOP

TOP VIEW

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

PINDESCRIPTION

^{of 150}°C and a board trace length of 750 mils.

Pin Number

FunctionalDescription

REF ⁽¹⁾

CLKA1⁽²⁾

CLKA2⁽²⁾

VDD

InputReferenceClock,5VoltTolerantInput

Clock Output for Bank A

3.3V Supply

GND

Ground

CLKB1⁽²⁾

CLKB2⁽²⁾

S2⁽³⁾

Clock Output for Bank B

Select Input, Bit 2

APPLICATIONS:

• SDRAM

• Telecom

S1⁽³⁾

Select Input, Bit 1

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

CLKB3⁽²⁾

CLKB4⁽²⁾

GND

Clock Output for Bank B

Ground

VDD

3.3V Supply

CLKA3⁽²⁾

CLKA4⁽²⁾

FBK

Clock Output for Bank A

PLLFeedbackInput

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

123 4 5 6 7...10

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