4.8
Transaction Termination................................................................................................ 4-21
4.8.1
4.8.2
4.8.3
Master Termination Initiated by the 21152..................................................... 4-22
Master Abort Received by the 21152.............................................................. 4-22
Target Termination Received by the 21152.................................................... 4-24
4.8.3.1 Delayed Write Target Termination Response .................................. 4-24
4.8.3.2 Posted Write Target Termination Response ..................................... 4-25
4.8.3.3 Delayed Read Target Termination Response ................................... 4-25
Target Termination Initiated by the 21152 ..................................................... 4-27
4.8.4.1 Target Retry ...................................................................................... 4-27
4.8.4.2 Target Disconnect.............................................................................4-28
4.8.4.3 Target Abort...................................................................................... 4-28
4.8.4
5
Address Decoding.......................................................................................................................... 5-1
5.1
5.2
Address Ranges ............................................................................................................... 5-1
I/O Address Decoding ..................................................................................................... 5-1
5.2.1
5.2.2
I/O Base and Limit Address Registers .............................................................. 5-2
ISA Mode.......................................................................................................... 5-3
5.3
5.4
Memory Address Decoding............................................................................................. 5-4
5.3.1
5.3.2
5.3.3
Memory-Mapped I/O Base and Limit Address Registers................................. 5-5
Prefetchable Memory Base and Limit Address Registers................................. 5-7
Prefetchable Memory 64-Bit Addressing Registers.......................................... 5-8
VGA Support................................................................................................................... 5-9
5.4.1
5.4.2
VGA Mode........................................................................................................ 5-9
VGA Snoop Mode............................................................................................. 5-9
6
7
Transaction Ordering ..................................................................................................................... 6-1
6.1
6.2
6.3
6.4
Transactions Governed by Ordering Rules ..................................................................... 6-1
General Ordering Guidelines........................................................................................... 6-2
Ordering Rules................................................................................................................. 6-3
Data Synchronization ...................................................................................................... 6-4
Error Handling ............................................................................................................................... 7-1
7.1
7.2
Address Parity Errors....................................................................................................... 7-1
Data Parity Errors ............................................................................................................ 7-2
7.2.1
7.2.2
7.2.3
7.2.4
Configuration Write Transactions to 21152 Configuration Space.................... 7-2
Read Transactions ............................................................................................. 7-2
Delayed Write Transactions.............................................................................. 7-3
Posted Write Transactions................................................................................. 7-5
7.3
7.4
Data Parity Error Reporting Summary ............................................................................ 7-7
System Error (SERR#) Reporting ................................................................................. 7-14
8
9
Exclusive Access............................................................................................................................ 8-1
8.1
8.2
8.3
Concurrent Locks ............................................................................................................ 8-1
Acquiring Exclusive Access Across the 21152............................................................... 8-1
Ending Exclusive Access................................................................................................. 8-3
PCI Bus Arbitration ....................................................................................................................... 9-1
9.1
9.2
Primary PCI Bus Arbitration ........................................................................................... 9-1
Secondary PCI Bus Arbitration ....................................................................................... 9-1
9.2.1
9.2.2
Secondary Bus Arbitration Using the Internal Arbiter...................................... 9-2
Secondary Bus Arbitration Using an External Arbiter...................................... 9-3
iv
21152 PCI-to-PCI Bridge Preliminary Datasheet
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