Datasheet > 2.5-VLVTTL

2.5-VLVTTL

更新时间： 2022-06-03 06:49:30

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描述
This chapterdescribes the electric characteristics, switching characteristics,and I/O timing for Cyclone III devices. A glossary is also included for your reference

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2.5-VLVTTL 数据手册

1–10

Chapter 1: Cyclone III Device Datasheet

Electrical Characteristics

Schmitt Trigger Input

Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,

nCE

CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the

input signal for improved noise immunity, especially for signal with slow edge rate.

Table 1–12 lists the hysteresis specifications across supported V_CCIOrange for Schmitt

trigger inputs in Cyclone III devices.

Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices

Symbol

Parameter

Conditions

Minimum

200

Typical

—

Maximum

Unit

V_CCIO= 3.3 V

—

_CCIO= 2.5 V

_CCIO= 1.8 V

200

—

Hysteresis for Schmitt trigger

input

V_SCHMITT

140

—

V_CCIO= 1.5 V

110

—

I/O Standard Specifications

The following tables list input voltage sensitivities (V_IHand V_IL), output voltage (V_OH

and V_OL), and current drive characteristics (I_OHand I_OL) for various I/O standards

supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O

standard specifications for Cyclone III devices.

(1), (2)

Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications

V_CCIO(V)

V_IL(V)

V_IH(V)

Max

V_OL(V)

V_OH(V)

I_OL

I_OH

I/O Standard

(mA)

Min

3.135

2.85

Typ

3.3

3.0

Max

3.465

Min

Max

0.8

Min

1.7

Max

0.45

0.2

Min

2.4

(3)

3.3-V LVTTL

—

3.6

–4

–2

(3)

3.3-V LVCMOS

3.6

V_CCIO– 0.2

2.4

(3)

3.0-V LVTTL

3.15 –0.3

V_CCIO+ 0.3

0.45

0.2

–4

3.0-V LVCMOS

2.85

V_CCIO– 0.2

0.1

–0.1

2.5-V LVTTL and

LVCMOS

2.375

1.71

1.425

1.14

2.85

2.5

1.8

1.5

1.2

3.0

2.625 –0.3

1.89 –0.3

1.575 –0.3

1.26 –0.3

0.7

1.7

3.6

0.4

2.0

–1

–2

(3)

1.8-V LVTTL and

LVCMOS

0.35 * 0.65 *

V_CCIOV_CCIO

V_CCIO

0.45

–

2.25

0.45

0.35 * 0.65 *

V_CCIOV_CCIO

0.25 *

V_CCIO

0.75 *

V_CCIO

1.5-V LVCMOS

1.2-V LVCMOS

3.0-V PCI

V_CCIO+ 0.3

–2

0.35 * 0.65 *

V_CCIO

0.25 *

V_CCIO

0.75 *

V_CCIO

–2

V_CCIO

0.3 *

V_CCIO

0.5 *

V_CCIO

3.15

—

V_CCIO+ 0.3 0.1 * V_CCIO0.9 * V_CCIO

1.5

–0.5

0.35*

V_CCIO

0.5 *

V_CCIO

3.0-V PCI-X

Notes to Table 1–13:

(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/O Standard”

in “Glossary” on page 1–27.

(2) AC load CL = 10 pF.

(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III

Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.

Cyclone III Device Handbook

Volume 2

July 2012 Altera Corporation

1...7 8 91011 12 13...34

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