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1SMC6.5AT3 PDF预览

1SMC6.5AT3

更新时间： 2024-02-16 10:15:45
品牌 Logo 应用领域
安森美 - ONSEMI 瞬态抑制器二极管光电二极管局域网
页数 文件大小 规格书
8页 73K
描述
1500 Watt Peak Power Zener Transient Voltage Suppressors

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1SMC6.5AT3 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：SMC, 2 PINReach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8541.10.00.50
风险等级：5.69其他特性：UL RECOGNIZED, HIGH RELIABILITY
最大击穿电压：7.98 V最小击穿电压：7.22 V
配置：SINGLE二极管元件材料：SILICON
二极管类型：TRANS VOLTAGE SUPPRESSOR DIODEJESD-30 代码：R-PDSO-C2
最大非重复峰值反向功率耗散：1500 W元件数量：1
端子数量：2封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性：UNIDIRECTIONAL
最大功率耗散：0.75 W认证状态：Not Qualified
最大重复峰值反向电压：6.5 V表面贴装：YES
技术：ZENER端子形式：C BEND
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

1SMC6.5AT3 数据手册

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1SMC5.0AT3 Series  
APPLICATION NOTES  
RESPONSE TIME  
minimum lead lengths and placing the suppressor device as  
close as possible to the equipment or components to be  
protected will minimize this overshoot.  
In most applications, the transient suppressor device is  
placed in parallel with the equipment or component to be  
protected. In this situation, there is a time delay associated  
with the capacitance of the device and an overshoot  
condition associated with the inductance of the device and  
the inductance of the connection method. The capacitive  
effect is of minor importance in the parallel protection  
scheme because it only produces a time delay in the  
transition from the operating voltage to the clamp voltage as  
shown in Figure 5.  
The inductive effects in the device are due to actual  
turn-on time (time required for the device to go from zero  
current to full current) and lead inductance. This inductive  
effect produces an overshoot in the voltage across the  
equipment or component being protected as shown in  
Figure 6. Minimizing this overshoot is very important in the  
application, since the main purpose for adding a transient  
suppressor is to clamp voltage spikes. The SMC series have  
a very good response time, typically < 1 ns and negligible  
inductance. However, external inductive effects could  
produce unacceptable overshoot. Proper circuit layout,  
Some input impedance represented by Z is essential to  
in  
prevent overstress of the protection device. This impedance  
should be as high as possible, without restricting the circuit  
operation.  
DUTY CYCLE DERATING  
The data of Figure 1 applies for non-repetitive conditions  
and at a lead temperature of 25°C. If the duty cycle increases,  
the peak power must be reduced as indicated by the curves  
of Figure 7. Average power must be derated as the lead or  
ambient temperature rises above 25°C. The average power  
derating curve normally given on data sheets may be  
normalized and used for this purpose.  
At first glance the derating curves of Figure 7 appear to be  
in error as the 10 ms pulse has a higher derating factor than  
the 10 µs pulse. However, when the derating factor for a  
given pulse of Figure 7 is multiplied by the peak power value  
of Figure 1 for the same pulse, the results follow the  
expected trend.  
http://onsemi.com  
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