™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Pin configuration
Table 1
Pin configuration (continued)
Pin No. Name
Function
3
4
5
6
7
8
IN
PWM driver input (active high)
Logic ground
GND1
VEE2
Power ground
OUTF / OUTFC
OUT
Additional driver output
Regular driver output
VCC2
Positive power supply output side
1
2
3
4
VCC1
/INF
VCC2
OUT
8
7
6
5
IN
OUTF
VEE2
GND1
Figure 3
Pinout standard configuration (top view)
1
2
3
4
VCC1
/INF
VCC2
OUT
8
7
6
5
IN
OUTFC
VEE2
GND1
Figure 4
Pinout clamp configuration (top view)
Pin description
•
VCC1: Logic input supply voltage with wide operating range from 3.3 V up to 15 V. This terminal is referenced
to GND1
•
•
GND1: Ground connection of input circuit. This is the reference point for the input side.
/INF: Inverted control signal for controlling the operation of output OUTF or OUTFC respectively. An internal
filter provides robustness against noise at terminal /INF. An internal weak pull-down resistor favors a low
level. This terminal is referenced to GND1
•
•
IN: Direct control signal for driver output. An internal filter provides robustness against noise at terminal IN.
An internal weak pull-down resistor favors off-state. This terminal is referenced to GND1
VCC2: Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close
to this supply pin. This terminal is referenced to VEE2.
Datasheet
6
v2.0
2021-04-09