Datasheet > 1894-32

1894-32

更新时间： 2023-12-20 18:44:29

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
51页	508K
描述
10Base-T/100Base-TX Integrated PHYceiver? with RMII Interface

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

1894-32 数据手册

ICS1894-32

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

PHYCEIVER

Pin Descriptions

Number

Name

Pin Description

Type¹

TP_AP

TP_AN

VSS

AIO

Twisted pair port A (for either transmit or receive) positive signal

Twisted pair port A (for either transmit or receive) negative signal

Ground Connect to ground.

Power 3.3V Power Supply

VDD

TP_BN

TP_BP

VDD

AIO

Twisted pair port B (for either transmit or receive) negative signal

Twisted pair port B (for either transmit or receive) positive signal

Power 3.3V Power Supply

AIO Transmit Current bias pin, connected to Vdd and ground via resistors (see

TCSR

“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).

VSS

Ground Connect to ground.

RESET_N

P2/INT

Input Hardware reset for the entire chip (active low)

IO/Ipd PHY address Bit 2 as input (during power on reset/hardware reset)

Interrupt output as output (default active low, can be programmed to active high)

MDIO

MDC

Management Data Input/Output

Input Management Data Clock

AMDIX/RXD3

IO/Ipu AMDIX enable as input (during power on reset/hardware reset)

Receive data Bit 3 in MII mode as output.

P3/RXD2

IO/Ipd PHY address Bit 3 as input (during power on reset/hardware reset)

Receive data Bit 2 in MII mode as output.

RXTRI/

RXD1

IO/Ipd RX tri-state enable as input (during power on reset/hardware reset)

Receive data Bit 1 in both RMII and MII mode as output.

FDPX/

RXD0

IO/Ipu Full duplex enable as input (during power on reset/hardware reset)

Receive data Bit 0 in both RMII and MII mode as output

RMII/RXDV

IO/Ipd RMII/MII select as input (during power on reset/hardware reset)

Receive data valid in MII mode and CRS_DV in RMII mode as output.

VDDIO

Power 3.3 V/1.8 V IO Power Supply.

ANSEL/

RXCLK

IO/Ipu Auto-negotiation enable as input (during power on reset/hardware reset)

Receive clock in MII mode as output.

NOD/

RXER

IO/Ipd Node select as input (during power on reset/hardware reset)

Receive error in MII/RMII mode as output

It is recommended to always pull this pin low on power-up or hardware reset.

SPEED/

TXCLK

IO/Ipu 10M/100M select as input (during power on reset/hardware reset)

Transmit clock in MII mode as output

TXEN

TXD0

Input Transmit enable in RMII/MII mode

Input Transmit data Bit 0 in RMII/MII mode

Power 3.3 V Power Supply

VDDD

TXD1

Input Transmit data Bit 1 in RMII/MII mode

Input Transmit data Bit 2 in MII mode

TXT2

TXD3

Input Transmit data Bit 3 in MII mode

REFOUT

REFIN

Output 25 MHz crystal output, floating in RMII mode

Input 25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode.

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32

REV M 021512

1 234 5 6 7...51

下载PDF

与1894-32相关器件

型号	品牌	描述	获取价格	数据表
1894-32KLF	IDT	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE	获取价格
1894-32KLFT	IDT	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE	获取价格
1894-40	RENESAS	10Base-T/100Base-TX Integrated PHYceiver? with RMII Interface	获取价格
1894-40KLF	IDT	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE	获取价格
1894-40KLFT	IDT	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE	获取价格
1894419	PHOENIX	Strip Terminal Block, 12A, 1 Row(s), 1 Deck(s)	获取价格