Datasheet > 1522MLF

1522MLF

更新时间： 2024-01-03 15:48:55

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
14页	452K
描述
SOIC-24, Tube

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数据手册

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1522MLF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	LEAD FREE, SOIC-24	针数：	24
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.68
其他特性：	DIFFERENTIAL O/PS; PHASE COMPARATOR GAIN O/PS	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3	长度：	15.24 mm
湿度敏感等级：	1	端子数量：	24
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	230 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
主时钟/晶体标称频率：	20 MHz	认证状态：	Not Qualified
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.493 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, VIDEO	Base Number Matches：	1

1522MLF 数据手册

ICS1522

User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator

TSD

Now, imagine that the programmed value of the divider

(really a prescaler) is increased by one for a single pass-

through that prescaler (think of this as “swallowing” a

feedback pulse). We will lose exactly one CLK period of

phase in the feedback path. The VCO will speed up

momentarily to compensate for that, and re-lock the loop.

Pixel-by-Pixel Adjustment of

Genlocking Phase(ICS1522 Application)

To understand the operation of the pixel-by-pixel phase

adjust-ment feature, imagine that the modulus of the on-

chip divider is equivalent to the graphics system overall

divide. Also, imagine that the overflow of the internal

divider occurs at the same time as the overflow of the

graphics system line counter. Initial synchronization is

accomplished by switching from the external feedback

source (graphics system HSYNC) to the internal feedback.

Let us assume that we are now using the internal divider.

In doing so, the graphics system will receive exactly one

extra CLK cycle, advancing the phase of the graphics

system HSYNC by one CLK period relative to the reference

HSYNC. In a similar fashion, we can decrease the

programmed value of the prescaler (“adding” a pulse) to

retard the phase of the graphics system. Additionally, sub-

pixel phase adjustment is provided through varying the

voltage at the FINE input pin.

24-Pin SOIC Package

Ordering Information

ICS1522M

Example:

ICS XXXX M

Package Type

M=SOIC, MT=SOIC/Tape and Reel, MLF=SOIC/Pb free, MLFT=SOIC/Pb free/Tape and Reel

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS=Standard Device

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.

IDT™ / ICS™ User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator

ICS1522

1...10 11 121314

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与1522MLF相关器件

型号	品牌	描述	获取价格	数据表
1522MLFT	IDT	Video Clock Generator, 230MHz, CMOS, PDSO24, LEAD FREE, SOIC-24	获取价格
15-22-R6G6C-A32-2T	EVERLIGHT	Chip LED with Bi-Color (Multi-Color)	获取价格
15-22-R6GHC-A01-2T	EVERLIGHT	Chip LED with Bi-Color (Multi-Color)	获取价格
15-22SDRSYGC/S530-A3/E2/TR8	EVERLIGHT	Dual Color LED, Super Deep Red/super Yellow Green, Water Clear, 2.7mm, ROHS COMPLIANT, SMD	获取价格
15-22SDRVGC/S530-A2	ETC	Chip LED with Bi-Color(Multi-Color)	获取价格
15-22SDRVGC/S530-A2/TR8	ETC	Chip LED with Bi-Color(Multi-Color)	获取价格

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