Datasheet > 1345CAPC

1345CAPC

更新时间： 2024-01-02 04:39:28

品牌	Logo	应用领域
杰尔 - AGERE		电信集成电路异步传输模式 ATM 时钟
页数	文件大小	规格书
12页	94K
描述
1345-Type Receiver with Clock Recovery and Data Retiming

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技术参数
数据手册

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1345CAPC 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	,	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.42	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
认证状态：	Not Qualified	标称供电电压：	5 V
电信集成电路类型：	ATM/SONET/SDH RECEIVER	温度等级：	INDUSTRIAL
Base Number Matches：	1

1345CAPC 数据手册

1345-Type Receiver with

Clock Recovery and Data Retiming

Data Sheet

January 2000

Description ^(continued)

Flag Output

The receiver converts optical signals in the range of

1.1 µm to 1.6 µm into retimed clock and data signals.

The clock and data outputs are raised-ECL (PECL)

logic levels. A CMOS-level flag output indicates when

there is a loss of optical signal.

When the optical input falls below the link status flag

switching threshold, the link status flag is deactivated

and its output logic level changes from a CMOS logic

HIGH to a CMOS logic LOW.

Squelched Data and Clock Outputs

The receiver requires a 5 V power supply for the ampli-

fier, logic, and PLL CRC circuits. The operating case

temperature range is –40 °C to +85 °C.

In some versions of the 1345 receiver (see Table 4),

when the link status flag is deactivated, the data and

clock outputs are squelched (stop outputting a signal).

When this occurs, the DATA, DATA, CLOCK, and

CLOCK outputs switch to a constant dc output voltage

level of 1.3 V.

Pin 10

Pin 10 on the 1345-Type receiver is not an internally

connected (NIC) pin. This definition allows the 1345 to

be used in most customer 20-pin receiver module

applications. Customer’s printed-wiring boards that are

designed with ground, +5 V, –5 V, or no connection to

this pin are all acceptable options. For those applica-

tions that require monitoring the photocurrent of the

PIN photodetector for power monitoring purposes,

there are versions of the 1345 that require +5 V or –5 V

applied to Pin 10. Check Tables 3 and 4 for ordering

information.

Nonsquelched Data and Clock Outputs

Agere Systems also manufactures nonsquelching ver-

sions of the 1345 receiver for those applications that

require the data and clock outputs to continue to func-

tion after the link status flag is deactivated. In those

versions of the receiver, when the link status flag is

deactivated, a signal will continue to appear at the

DATA, DATA, CLOCK, and CLOCK outputs. See Table 4

for nonsquelching codes.

OPTIONAL VPIN

5 V

FLAG FLAG

DATA DATA

FILTER

SILICON BIPOLAR

DECISION CIRCUIT

InGaAs

SILICON BIPOLAR

LIMITING AMPLIFIER

PREAMPLIFIER

PLL TIMING

RECOVERY UNIT

CLOCK CLOCK

1-724(C)

Figure 1. Block Diagram

Agere Systems Inc.

123 4 5 6 7...12

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