Datasheet > 1345FNPC

1345FNPC

更新时间： 2024-02-20 15:15:32

品牌	Logo	应用领域
杰尔 - AGERE		电信集成电路异步传输模式 ATM 时钟
页数	文件大小	规格书
12页	94K
描述
1345-Type Receiver with Clock Recovery and Data Retiming

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技术参数
数据手册

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1345FNPC 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	,	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.42	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
认证状态：	Not Qualified	标称供电电压：	5 V
电信集成电路类型：	ATM/SONET/SDH RECEIVER	温度等级：	INDUSTRIAL
Base Number Matches：	1

1345FNPC 数据手册

Data Sheet

January 2000

1345-Type Receiver with

Clock Recovery and Data Retiming

Applications

■ Telecommunications:

— Inter- and intraoffice SONET/ITU-T SDH

— Subscriber loop

— Metropolitan area networks

■ High-speed data communications

Description

Operating at 1.3 µm or 1.55 µm wavelengths and at

155 Mbits/s or 622 Mbits/s, the versatile 1345-Type Receiver is

manufactured in a 20-pin, plastic DIP with a multimode fiber

pigtail.

The 1345-Type fiber-optic receiver is designed for

use in transmission systems or medium- to high-

speed data communication applications. Used in

intermediate- and long-reach applications, the

receiver operates at the SONET OC-3 or OC-12 data

rate as well as the ITU-T synchronous digital hierar-

chy (SDH) rate of STM-1 or STM-4, depending on

the receiver model chosen. The receiver meets all

present Telcordia Technologies GR-253-CORE

requirements, the current ANSI T1X1.5 intraoffice

specifications, and the ITU-T G.957 and G.958 rec-

ommendations. Compact packaging, a high level of

integration, and a wide dynamic range make these

receivers ideal for data communications.

Features

■ Backward compatible with 1330 family

■ Space-saving, self-contained, 20-pin plastic DIP

■ Silicon based ICs

■ Single 5 V power supply operation including

photocurrent monitor capability

■ Exceeds all SONET (GR-253-CORE) and ITU-T

G.958 jitter requirements

Manufactured in a 20-pin DIP, the receiver consists of

a planar InGaAs PIN photodetector, a silicon pream-

plifier, a silicon bipolar limiting amplifier that converts

the small signal to ECL levels, a timing recovery unit

to recover the clock, and a silicon bipolar decision cir-

cuit.

■ Clocked decision circuit

■ Regenerated differential clock signal

■ Wide dynamic range

■ Qualified to meet the intent of Telcordia Technolo-

gies™ reliability practices

■ Operates at data rates of 155 Mbits/s or

622 Mbits/s

■ Positive ECL (PECL) data outputs

■ CMOS (TTL) link-status flag output

■ Operation at 1.3 µm or 1.55 µm wavelengths

■ Operating temperature range of –40 °C to +85 °C

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