Datasheet > 11257-804

11257-804

更新时间： 2024-01-07 16:20:21

品牌	Logo	应用领域
其他 - ETC		逻辑集成电路光电二极管驱动时钟
页数	文件大小	规格书
19页	384K
描述
LOW-SKEW CLOCK FANOUT BUFFER ICs

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技术参数
数据手册

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11257-804 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G28
长度：	17.9 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	28	实输出次数：	14
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	传播延迟（tpd）：	5 ns
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	Base Number Matches：	1

11257-804 数据手册

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April 1999

3.2

3.0 Programming Information

A logic-one written to a valid bit location turns on the as-

signed output clock. Likewise, a logic-zero written to a

valid bit location turns off the assigned output clock.

Table 2: Clock Enable

CONTROL INPUTS

CLOCK OUTPUTS (MHz)

Any unused or reserved register bits should be cleared to

zero.

SDRAM_0:17

Serial bits are written to this device in the order shown in

Table 3.

tristate

CLK_IN

Table 3: Register Summary

3.1

Power-Up Initialization

SERIAL BIT

DATA BYTE

CLOCK OUTPUT

All outputs are enabled and active upon power-up, and all

output control register bits are initialized to one.

(MSB)

SDRAM_7

SDRAM_6

SDRAM_5

SDRAM_4

SDRAM_3

SDRAM_2

SDRAM_1

SDRAM_0

SDRAM_15

SDRAM_14

SDRAM_13

SDRAM_12

SDRAM_11

SDRAM_10

SDRAM_9

SDRAM_8

SDRAM_17

SDRAM_16

Reserved

The outputs must be configured at power-up and are not

expected to be configured during normal operation. Inac-

tive outputs are held low and are disabled from switching.

Byte 0

SDRAM Control Register 0

3.1.1 Unused Outputs

Outputs that are not used in versions of this device with a

reduced pinout are still operational internally. To reduce

power dissipation and crosstalk effects from the unloaded

outputs, it is recommended that these outputs be shut off

via the Control Registers.

(LSB)

(MSB)

Byte 1

SDRAM Control Register 1

(LSB)

(MSB)

Byte 2

Reserved

SDRAM Control Register 2

Reserved

(LSB)

Reserved

4.5.99

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1 234 5 6 7...19

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