Datasheet > 11257-801

11257-801

更新时间： 2024-01-11 21:47:41

品牌	Logo	应用领域
其他 - ETC		逻辑集成电路光电二极管驱动时钟
页数	文件大小	规格书
19页	384K
描述
LOW-SKEW CLOCK FANOUT BUFFER ICs

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11257-801 技术参数

生命周期：	Transferred	包装说明：	0.300 INCH, SSOP-48
Reach Compliance Code：	unknown	风险等级：	5.66
Is Samacsys：	N	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G48	长度：	15.875 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	48
实输出次数：	18	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：	5 ns	认证状态：	Not Qualified
座面最大高度：	2.794 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	宽度：	7.5 mm
Base Number Matches：	1

11257-801 数据手册

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April 1999

Series termination adds no dc loading to the driver, and pacitance, and the number of connected devices with

requires less power than other resistive termination their associated input currents.

methods. Further, no extra impedance exists from the

signal line to a reference voltage, such as ground.

Control of the clock and data lines is done through open

drain/collector current-sink outputs, and thus requires

As shown in Figure 19, the sum of the driver’s output im- external pull-up resistors on both lines. A guideline is

pedance (z_O) and the series termination resistance (R_S)

must equal the line impedance (z_L). That is,

t_r

R_P<

2×C_bus

R_S= z_L− z_O

where t_ris the maximum rise time (minus some margin)

and C_busis the total bus capacitance. Assuming an I²C

device on each DIMM, an I²C controller, the clock buffer,

and two other bus devices results in values in the 5kΩ to

7kΩ range. Use of a series resistor to provide protection

against high voltage spikes on the bus will alter the val-

ues for R_P.

Note that when the source impedance (z_O+R_S) is

matched to the line impedance, then by voltage division

the incident wave amplitude is one-half of the full signal

amplitude.

(z_O+ R_S)

V_i= V

(z_O+ R_S) + z_L

The full signal amplitude may take up to twice as long as

the propagation delay of the line to develop, reducing

noise immunity during the half-amplitude period. Note

also that the voltage at the receive end must add up to a

signal amplitude that meets the receiver switching

thresholds. The slew rate of the signal is also reduced

due to the additional RC delay of the load capacitance

and the line impedance. Also note that the output driver

impedance will vary slightly with the output logic state

(high or low).

Figure 20: Connections to the Serial Bus

R_P

SDA

SCL

R_S

(optional)

R_S

(optional)

R_S

(optional)

R_S

(optional)

Data In

Clock Out

Clock In

Data Out

8.2

Dynamic Power Dissipation

TRANSMITTER

RECEIVER

High-speed clock drivers require careful attention to

power dissipation. Transient power (P_T) consumption can

be derived from

8.3.1 For More Information

P = V_DD²×C_load× f_CLK× N_SW

More detailed information on serial bus design can be

obtained from SMBus and I²C Bus Design, available from

the Intel Corporation at http://www.intel.com.

Information on the I²C-bus can be found in the document

The I²C-bus And How To Use It (Including Specifica-

tions), available from Philips Semiconductors at

http://www-us2.semiconductors.philips.com.

where C_loadis the load capacitance, V_DDis the supply

voltage, f_CLKis the clock frequency, and N_swis the

number of switching outputs.

The internal heat (junction temperature, T_J) generated by

the power dissipation can be calculated from

Additional information on the System Management Bus

can be found in the System Management Bus Specifica-

tion, available from the Smart Battery System

Implementers’ Forum at http://www.sbs-forum.org.

T_J= Θ_JA× P +T_A

where Θ_JAis the package thermal resistance, T_Ais the

ambient temperature, and P_Tis derived above.

8.3

Serial Communications

Connection of devices to a standard-mode implementa-

tion of either the I²C-bus or the SMBus is similar to that

shown in Figure 20. Selection of the pull-up resistors (R_P)

and the optional series resistors (R_S) on the SDA and

SCL lines depends on the supply voltage, the bus ca-

4.5.99

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1...16 17 1819

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11257-802	ETC	LOW-SKEW CLOCK FANOUT BUFFER ICs	获取价格
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11257-804	ETC	LOW-SKEW CLOCK FANOUT BUFFER ICs	获取价格
11257-806	ETC	LOW-SKEW CLOCK FANOUT BUFFER ICs	获取价格
11257-811	ETC	LOW-SKEW CLOCK FANOUT BUFFER ICs	获取价格
11257-812	ETC	LOW-SKEW CLOCK FANOUT BUFFER ICs	获取价格

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