Datasheet > 10M08DAU324I6

10M08DAU324I6

更新时间： 2023-01-02 22:19:37

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
14页	604K
描述
Field Programmable Gate Array, PBGA324, 15 X 15 MM, 0.80 MM PITCH, UBGA-324

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10M08DAU324I6 数据手册

M10-OVERVIEW

2014.09.22

MAX 10 ADC Vertical Migration Support

Figure 3: ADC Vertical Migration Across MAX 10 Devices—Preliminary

The arrows indicate the ADC migration paths. The devices included in each vertical migration path are

shaded.

Package

F256

Device

M153

U169

U324

E144

F484

F672

10M04

10M08

10M16

10M25

10M40

10M50

Dual ADC Device: Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins.

Single ADC Device: Single ADC supports 1 dedicated analog input pin and 16 dual function pins.

Table 7: Pin Migration Conditions for ADC Migration

Source

Target

Migratable Pins

Single ADC device

Dual ADC device

Single ADC device

Dual ADC device

Single ADC device

Dual ADC device

Single ADC device

You can migrate all ADC input pins

•

One dedicated analog input pin.

Eight dual function pins from the ADC1

block of the source device to the ADC1

block of the target device.

Logic Elements and Logic Array Blocks

The LAB consists of 16 logic elements and a LAB-wide control block. An LE is the smallest unit of logic in

the MAX 10 device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register,

and output logic. The four-input LUT is a function generator that can implement any function with four

variables.

MAX 10 FPGA Device Overview

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