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10AX090N2F40E1SG PDF预览

10AX090N2F40E1SG

更新时间： 2024-02-25 22:27:13
品牌 Logo 应用领域
英特尔 - INTEL 栅可编程逻辑
页数 文件大小 规格书
110页 1391K
描述
Field Programmable Gate Array, 900000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517

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10AX090N2F40E1SG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA, BGA1517,39X39,40Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.45
JESD-30 代码：S-PBGA-B1517长度：40 mm
输入次数：600逻辑单元数量：900000
输出次数：600端子数量：1517
最高工作温度：100 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA1517,39X39,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：0.9 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：3.5 mm
子类别：Field Programmable Gate Arrays最大供电电压：0.93 V
最小供电电压：0.87 V标称供电电压：0.9 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：40 mm
Base Number Matches：1

10AX090N2F40E1SG 数据手册

 浏览型号10AX090N2F40E1SG的Datasheet PDF文件第103页浏览型号10AX090N2F40E1SG的Datasheet PDF文件第104页浏览型号10AX090N2F40E1SG的Datasheet PDF文件第105页浏览型号10AX090N2F40E1SG的Datasheet PDF文件第107页浏览型号10AX090N2F40E1SG的Datasheet PDF文件第108页浏览型号10AX090N2F40E1SG的Datasheet PDF文件第109页 
A10-DATASHEET  
2015.12.31  
106  
Document Revision History  
Date  
Version  
Changes  
•
•
Made the following changes to the "Transceiver Performance for Arria 10 GT Devices" section.  
•
•
Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.  
Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and  
Receiver Data Rate Performance" table.  
•
•
•
Changed the minimum frequency in the "ATX PLL Performance" table.  
Changed the minimum frequency in the "Fractional PLL Performance" table.  
Changed the minimum frequency in the "CMU PLL Performance" table.  
Added voltage condition to the maximum peak-to-peak diff p-p after configuration and to the VICM specifi‐  
cations in the "Receiver Specifications" table.  
•
•
•
Changed the voltage conditions for VOCM in the "Transmitter Specifications" table.  
Changed the VOD/VCCT Ratios in the "Typical Transmitter VOD Settings" table.  
Added the "Transceiver Clock Network Maximum Data Rate Specifications" table.  
January 2015  
2015.01.23  
•
•
Added a note in the "Transceiver Power Supply Operating Conditions" section.  
Made the following changes to the "Reference Clock Specifications" table:  
•
•
•
•
Added the input reference clock frequency parameters for the CMU PLL, ATX PLL, and fPLL PLL.  
Changed the maximum specification for rise time and fall time.  
Added the VICM (AC and DC coupled) parameters.  
Changed the maximum value for Transmitter REFCLK Phase Noise (622 MHz) when ≥ 1 MHz.  
•
•
Changed the Min, Typ, and Max values for the reconfig_clksignal in the "Transceiver Clocks Specifica‐  
tions" table.  
Made the following changes to the "Receiver Specifications" table:  
•
•
Added the maximum peak-to-peak differential input voltage after device configuration specifications.  
Changed the minimum specification for the minimum differential eye opening at receiver serial input  
pins parameter.  
•
Removed the 120-ohm and 150-ohm conditions for the differential on-chip termination resistors  
parameter.  
•
•
Added the VICM (AC and DC coupled) parameter.  
Added the Programmable DC Gain parameter.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
1...103104105106107108109110

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