Datasheet > 1024-60LH/883

1024-60LH/883

更新时间： 2022-11-25 13:07:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
12页	148K
描述
In-System Programmable High Density PLD

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数据手册

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1024-60LH/883 数据手册

Specifications ispLSI 1024/883

External Timing Parameters

Over Recommended Operating Conditions

-60

DESCRIPTION¹

UNITS

TEST

PARAMETER

COND.

MIN. MAX.

–

Data Propagation Delay, 4PT bypass, ORP bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with Internal Feedback³

–

pd1

pd2

MHz

max (Int.)

max (Ext.)

max (Tog.)

su1

Clock Frequency with External Feedback

Clock Frequency, Max Toggle⁴

–

(

)

tsu2 + tco1

–

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

GLB Reg. Hold Time after Clock, 4 PT bypass

GLB Reg. Setup Time before Clock

–

co1

–

su2

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

–

co2

–

22.5

–

rw1

14 Input to Output Enable

–

15 Input to Output Disable

–

dis

16 Ext. Sync. Clock Pulse Duration, High

17 Ext. Sync. Clock Pulse Duration, Low

–

18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

2.5

8.5

–

su5

–

Table 2-0030-24 mil

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-Bit loadable counter using GRP feedback.

4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

5. Reference Switching Test Conditions Section.

1 2 3 456 7 8...12

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