Datasheet > 1024-60LH/883

1024-60LH/883

更新时间： 2022-11-25 13:07:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
12页	148K
描述
In-System Programmable High Density PLD

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1024-60LH/883 数据手册

Specifications ispLSI 1024/883

Functional Block Diagram

Figure 1.ispLSI 1024/883 Functional Block Diagram

RESET

Generic

Logic Blocks

(GLBs)

IN 5

IN 4

I/O 47

I/O 46

I/O 0

I/O 45

I/O 1

I/O 44

I/O 2

I/O 3

I/O 43

I/O 42

I/O 41

I/O 4

I/O 5

I/O 40

Global

Routing

Pool

I/O 6

I/O 7

I/O 39

I/O 38

I/O 37

I/O 36

(GRP)

I/O 8

I/O 9

I/O 10

I/O 11

I/O 35

I/O 34

I/O 33

I/O 32

I/O 12

I/O 13

I/O 14

I/O 15

SDI/IN 0

SDO/IN 1

CLK 0

CLK 1

CLK 2

Clock

Distribution

Network

IOCLK 0

IOCLK 1

Megablock

Output Routing Pool (ORP)

Input Bus

ispEN

SCLK/IN 2

MODE/IN 3

I/O I/O I/O I/O

16 17 18 19

I/O I/O I/O I/O

20 21 22 23

I/O I/O I/O I/O

24 25 26 27

I/O I/O I/O I/O

28 29 30 31

0139D_1024.eps

The device also has 48 I/O cells, each of which is directly TheGRPhasasitsinputstheoutputsfromalloftheGLBs

connected to an I/O pin. Each I/O cell can be individually and all of the inputs from the bi-directional I/O cells. All of

programmed to be a combinatorial input, registered in- these signals are made available to the inputs of the

put, latched input, output or

bi-directional GLBs. Delays through the GRP have been equalized to

I/O pin with 3-state control. Additionally, all outputs are minimize timing skew.

polarity selectable, active high or active low. The signal

Clocks in the ispLSI 1024/883 device are selected using

levelsareTTLcompatiblevoltagesandtheoutputdrivers

can source 4 mA or sink 8 mA.

theClockDistributionNetwork.Fourdedicatedclockpins

(Y0, Y1, Y2 and Y3) are brought into the distribution

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

IOCLK 0 and IOCLK 1) are provided to route clocks to the

GLBs and I/O cells. The Clock Distribution Network can

alsobedrivenfromaspecialclockGLB (B4ontheispLSI

1024/883 device). The logic of this GLB allows the user

to create an internal clock from a combination of internal

signals within the device.

Eight GLBs, 16 I/O cells, two dedicated inputs and one

ORP are connected together to make a Megablock (see

figure 1). The outputs of the eight GLBs are connected

toaset of 16universalI/O cellsby theORP. TheI/O cells

within the Megablock also share a common Output

Enable (OE) signal. The ispLSI 1024/883 device con-

tains three of these Megablocks.

123 4 5 6 7...12

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