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100397

更新时间: 2024-11-18 22:37:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
13页 132K
描述
Quad Differential ECL/TTL Translating Transceiver with Latch

100397 数据手册

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January 1992  
Revised August 2000  
100397  
Quad Differential ECL/TTL Translating Transceiver  
with Latch  
General Description  
Features  
Differential ECL input/output structure  
The 100397 is a quad latched transceiver designed to con-  
vert TTL logic levels to differential F100K ECL logic levels  
and vice versa. This device was designed with the capabil-  
ity of driving a differential 25ECL load with cutoff capabil-  
ity, and will sink a 64 mA TTL load. The 100397 is ideal for  
mixed technology applications utilizing either an ECL or  
TTL backplane.  
64 mA FAST TTL outputs  
25differential ECL outputs with cut-off  
Bi-directional translation  
2000V ESD protection  
Latched outputs  
The direction of translation is set by the direction control  
pin (DIR). The DIR pin on the 100397 accepts F100K ECL  
logic levels. An ECL LOW on DIR sets up the ECL pins as  
inputs and TTL pins as outputs. An ECL HIGH on DIR sets  
up the TTL pins as inputs and ECL pins as outputs.  
3-STATE outputs  
Voltage compensated operating range = −4.2V to 5.7V  
A LOW on the output enable input pin (OE) holds the ECL  
output in a cut-off state and the TTL outputs at a high  
impedance level. A HIGH on the latch enable input (LE)  
latches the data at both inputs even though only one output  
is enabled at the time. A LOW on LE makes the latch trans-  
parent.  
The cut-off state is designed to be more negative than a  
normal ECL LOW level. This allows the output emitterfol-  
lowers to turn off when the termination supply is 2.0V, pre-  
senting a high impedance to the data bus. This high  
impedance reduces termination power and prevents loss of  
low state noise margin when several loads share the bus.  
The 100397 is designed with FAST TTL output buffers,  
featuring optimal DC drive and capable of quickly charging  
and discharging highly capacitive loads. All inputs have  
50 Kpull-down resistors.  
Ordering Code:  
Order Number Package Number  
Package Description  
100397PC  
100397QC  
100397QI  
N24E  
V28A  
V28A  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
Industrial Temperature Range (40°C to +85°C)  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
FAST is a registered trademark of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010971  
www.fairchildsemi.com  

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