Datasheet > ZSSC3026-KIT

ZSSC3026-KIT

更新时间： 2024-01-24 17:05:24

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
47页	905K
描述
Low-Power, High-Resolution 16-Bit Sensor Signal Conditioner

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ZSSC3026-KIT 数据手册

ZSSC3027 Datasheet

A dynamic power-on-reset circuit is implemented in order to achieve minimum current consumption in idle mode.

The VDD low level and the subsequent rise time and VDD rising slope must meet the requirements in Table 1.1 to

guarantee an overall IC reset; lower VDD low levels allow slower rising of the subsequent on-ramp of VDD. Other

combinations might also be possible. For example, the reset trigger can be influenced by increasing the power-

down time and lowering the VDD rising slope requirement.

Table 1.3 Requirements for VDD Power-on Reset

PARAMETER

Power Down Time (duration of VDD Low Level)

VDD Low Level

SYMBOL

t_SPIKE

MIN

TYP

MAX

UNIT

µs

0.2

VDD_low

SR_VDD

VDD Rising Slope

V/ms

1.3. Electrical Parameters

All parameter values are valid only under the specified operating conditions. All voltages are referenced to Vss.

Table 1.4 Electrical Parameters

Note: See important table notes at the end of the table.

Parameter

Symbol

Conditions/Comments

Min

Typ

Max

Unit

Supply

Bridge Supply Voltage,

ADC Reference Voltage

V_DDB

Internally generated

1.60

1.67

1.74

Active State, average

Sleep State, idle current

V_DD= 1.8V

930

1500

250

µA

Current Consumption

I_VDD

Power Supply Rejection

20·log₁₀(V_DD/V_DDB

)

PSR_VDD

V_DD,prog

I_VDD,prog

V_DD= 2V

(see section 1.4)

Memory Program Voltage

Mean Program Current

Required voltage level at VDD pin

2.9

3.6

Mean current consumption during

multiple-time memory (MTP)

programming cycle at VDD

MTP program at VDD pin,

dynamic switch-on current draw

Peak Program Current

I_prog,max

April 20, 2016

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