Enhanced PCI Bus Multimedia Controller
3.0 PIN DESCRIPTIONS
Symbol
PCI Interface (48 pins)
AD[31:0]
C/BE[3:0]
PAR
Type [1]
Direction
Description
3-state
3-state
3-state
3-state*
3-state*
3-state*
3-state*
3-state*
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Multiplexed address and data bus pins.
Bus commands or byte enables.
Even parity bit for AD31..0 and C/BE[3:0].
FRAME
TRDY
PCI cycle frame.
PCI target ready indicator.
IRDY
PCI initiator ready.
STOP
Indicates a target request to stop the current data transfer.
DEVSEL
IDSEL
PCI device select, indicates that the target has decoded its address.
PCI initialization device select. Used as a chip-select to the ZR36057’s configuration space.
REQ
3-state
3-state
I
O
PCI bus request.
PCI bus grant.
PCI clock.
GNT
I
PCICLK
PCIRST
I
I
I
PCI reset. When active, all ZR36057 output pins are tri-stated. A low to high transition puts the
ZR36057 into its power-on reset state. Minimum active low duration is 3 PCI clocks.
INTA
open drain
O
PCI interrupt request A. A low level on this signal requests an interrupt from the host.
Digital Video Bus Interface (32 pins)
Y[7:0]/R[7:0]
UV[7:0]/G[7:0]
B[7:0]
3-state
I/O
I/O
I/O
I
Luminance/Red video lines.
3-state
Chrominance/Green video lines.
3-state
Blue video lines.
VCLKx2
VCLK
I
Double frequency video bus clock.
I
I
Digital video bus clock. Used as a qualifier to VCLKx2. Must be synchronized to VCLKx2.
Digital video bus horizontal sync.
HSYNC
VSYNC
FI
3-state
I/O
I/O
I
3-state
Digital video bus vertical sync.
I
Digital video bus field indicator (top/bottom).
Active low Pixel Enable output to the ZR36016.
Active low Strip Memory Overflow/Underflow signal from the ZR36016.
Active high Start process output to the ZR36016.
PXEN
O
I
O
RTBSY
START
I
O
O
GuestBus Interface (25 pins)
GCS[7:0]
GADR[2:0]
GDAT[7:0]
GRD
O
O
O
I/O
O
O
I
Active low chip-select output to guest bus devices.
Address outputs to guest bus devices.
Guest data bus .
O
3-state
O
O
I
Active low read output to guest bus devices.
Active low write output to guest bus devices.
Active high “guest ready” input.
GWR
GRDY
GWS
I
I
Guest Wait-State indication. Assertion of this active-low input allows the guest device to extend
the GuestBus write (or read) cycle until it is capable of latching-in (or providing) the data.
GIRQ[1:0]
I
I
Positive-edge-sensitive interrupt request inputs from one or two of the guest bus slave devices.
CodecBus Interface (11 pins)
CODE[7:0]
CEND
3-state
I/O
Code Bus connected to the ZR36050.
I
I
I
I
Active low End of field process indication from the ZR36050.
Active low Code Bus active cycle signal from the ZR36050.
Active low Code FIFO Busy indication to the ZR36050.
CCS
CBUSY
O
O
I2C Bus Interface (2 pins)
SDA OD
I/O
I2C bus data
7
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