Datasheet > ZR36015PQC-30

ZR36015PQC-30

更新时间： 2024-02-23 09:15:08

品牌	Logo	应用领域
其他 - ETC		转换器栅
页数	文件大小	规格书
27页	168K
描述
RASTER TO BLOCK CONVERTER

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技术参数
数据手册

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ZR36015PQC-30 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP100,.63SQ,20	针数：	100
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
功能数量：	1	端子数量：	100
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	RECTANGULAR
封装形式：	FLATPACK	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	3.4 mm
子类别：	Other Consumer ICs	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

ZR36015PQC-30 数据手册

PRELIMINARY

ZR36015

■ VHeight(12:0):Verticle height of the active image area. The

maximum setting for Height(12:0) is 8191. Setting

Height(12:0) to ‘0’ in encode mode, lets the Height of the

active image area be determined by the non-active point of

VEN.

Operating States

The ZR36015 has four Operating States; Reset, Idle, Compres-

sion and Expansion.

Reset State

Address Pointer Value

Window Setting Value

HDelay(7:0)

While the RESET input is asserted, the ZR36015 is in the Reset

State. In this state the PXDATA and BDATA busses are high

impedance, and the DSYNC, STOP, EOS signals are high

impedance.

HDelay(12:8)

HWidth(7:0)

HWidth(14:0)

VDelay(7:0)

After a RESET, the ZR36015 will be in the IDLE state.

Idle State

After a Soft RESET, or after the RESET input signal has been

applied, or at the end of a compression or expansion process,

the ZR36015 will be in the IDLE state. In the IDLE state, no

active processing is taking place, and the PXDATA bus is high

impedance (the bus drivers for the Coder Interface are con-

trolled by the COE signal).

VDelay(12:8)

VWidth(7:0)

VWidth(13:8)

Number of Lines(7:0)

Number of Lines(13:8)

While in the IDLE state, the ZR36015 Configuration Register

Tables can be loaded with the values to select the desired active

image area. Also, the Mode Register is loaded with the desired

Mode of operation, and the number of lines table can be read

1. Assigned to LSB’s of PIXDATA(7:0)

HEN

To leave the IDLE state and enter one of the processing states

(compression or expansion), the GO bit in the Mode registe is

set.

Enable Area

Compression

When the GO bit is set to “1”, and the EDC bit equals “1”, then

the ZR36015 enters the Compression State.

Acitve Image

Area

Setting the GO bit results in the BSY bit in the mode register

being set.

HDelay

HWidth

Once the GO bit is set, then on the falling edge of the Verticle

Sync Signal (VEN), the BSY output signal will be set. The BSY

bit (and output signal) will stay set until the end of the Compres-

sion process. The hardware can monitor the BSY signal, to

determine when the Compression process has completed. Note

that the GO bit must be set at least three SYSCLK cycles before

the VEN goes from High to Low (see figure ???).

Figure 4. Active Image Area

Number of Lines Table:

The Number of Lines Table holds the number of lines processed

in encoding by the ZR36015.

Following the above, the ZR36015 monitors the VEN input to

detect the transiton of VEN from low to high. This indicates the

beginning of the image to be processed The next VDelay lines

of data are ignored in order to reach the “active image area”.

Then the next VWidth lines of data are processed.

The HEN input synchronizes the line by line transfers of data into

the ZR36015. On the rise of HEN, the next HDelay pixels are

ignored in order to reach the “active image area”. Then the next

HWidth pixels are procesed.

1 2 3 456 7 8...27

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