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ZR36015PQC-30 PDF预览

ZR36015PQC-30

更新时间: 2024-01-06 07:06:32
品牌 Logo 应用领域
其他 - ETC 转换器
页数 文件大小 规格书
27页 168K
描述
RASTER TO BLOCK CONVERTER

ZR36015PQC-30 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PQFP-G100长度:20 mm
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
认证状态:Not Qualified座面最大高度:3.4 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

ZR36015PQC-30 数据手册

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PRELIMINARY  
ZR36015  
SIGNAL DESCRIPTION  
1
Name  
Type  
Function  
PXDATA(15:0)  
B
Pixel side data bus. Input for compression and output for expansion. High impedance during RESET or IDLE modes.  
When SPH is active (High), PXDATA(7:0) is controlled by the Host Interface. It will be high impedance except during  
a Host read access, in which case it will be driven. The state of PXDATA(15:8) follows that of PXDATA(7:0) in this  
case but is unused.  
HEN  
I
Active High Horizontal enable signal (HDelay starts counting from the rise of HEN)  
Active High Verticle enable signal (VDelay starts counting from the rise of VEN)  
System clock (active on rising edge).  
VEN  
I
SYSCLK  
MADD(15:0)  
MDATA(15:0)  
MWE  
I
O
B
O
O
B
Address output for the strip memory. Up to 64K x 16 bits of SRAM is addressable.  
Data bus for the strip memory. Memory A is assigned to MDATA(7:0), and Memory B is assigned to MDATA(15:8).  
Active Low: Write enable for the Strip Memory.  
MOE  
Active Low: Output enable for the Strip Memory.  
DSYNC  
Active Low: Sync. signal for 64 byte block of data. Output during compression and input during expansion. In  
compression, DSYNC marks the start of an 8x8 image data block and should appear as an output one SYSCLK cycle  
before the first image data of a block. During expansion DSYNC is input on SYSCLK before the first image data of  
a sample block. The width of DSYNC is one SYSCLK. (Connect directly to ZR36050 DSYNC signal).  
STOP  
EOS  
B
B
Active Low: Stop sending/receiving. During compression, this signal is an input which indicates that the CODEC is  
busy, and the ZR36015 should stop sending data. During expansion, this signal is an output indicating the ZR36015  
is not ready to receive data, and for the CODEC to stop sending data. (Connect directly to ZR36050 STOP signal).  
Active Low: Signal indicates the end of each scan. Output during compression and input during expasion. In  
compression, EOS is output together with the last image data sample of the last block of each scan. In expansion,  
EOS is input together with the last image data sample of the last block of each scan. (Connect directly to ZR36050  
EOS signal).  
BDATA(7:0)  
B/Z  
Data bus interface with the Coder. Output for compression and input for expansion. High impedance during reset.  
Otherwise, the direction of the bus is determined by the COE input. (Connect directly to ZR36050 PIXEL(11:4) bus.)  
ADD(1:0)  
WR  
I
I
Address select for Host access to internal registers. Enabled when SPH is high.  
Active Low: Write strobe for Host loading of internal registers and tables. Data is writtern on the rising edge of WR.  
WR is enabled when SPH is high.  
RD  
I
O
I
Active Low: Read strobe for Host reading of internal registers and tables. RD is enabled when SPH is high.  
Active Low: CBSY indicates that the ZR36015 is not ready for the next strip of data.  
CBSY  
COE  
Coder bus output enable signal. HIGH for Compression Mode (enabling the output drivers for the CDATA bus, EOS  
signal and DSYNC signal. . LOW for Expansion mode (enabling the output drivers for the STOP signal). (Connect  
directly to ZR36050 COMP signal).  
BSY  
O
Active Low: BSY is active when the ZR36015 is processing an image. Before setting hte GO bit in the Mode Register,  
BSY should be inactive.  
CLKCSC  
SPH  
O
I
Clock output for ZR36011 Color Space Converter. Used to synchronize data transfers.  
Active High: Select host access to the ZR36015 via the PXDATA(7:0) data bus. Enables the WR, RD inputs.  
Active HIGH; Indicates active (windowed) image area.  
WINDOW  
RESET  
O
I
Asynchronous Active LOW reset. All bi-directional signals are tri-stated when this signal is active. After RESET , the  
ZR36015 will be in idle mode (GO bit cleared) and the PXDATA bus will continue to behigh impedance until the GO  
bit is set .  
V
V
Power terminal.  
Ground terminal.  
DD  
SS  
1. I = Input, O = Output, B = Bidirectional, Z = High Impedance.  
2

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