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ZPSD301V-20J PDF预览

ZPSD301V-20J

更新时间: 2024-02-21 22:15:20
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
页数 文件大小 规格书
85页 687K
描述
Low Cost Field Programmable Microcontroller Peripherals

ZPSD301V-20J 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP针数:44
Reach Compliance Code:not_compliant风险等级:5.64
Is Samacsys:N最长访问时间:2e-7 ns
JESD-30 代码:S-PQFP-G44JESD-609代码:e0
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP44,.63SQ,40
封装形状:SQUARE封装形式:FLATPACK
电源:3 V认证状态:Not Qualified
ROM大小(位):256 Bits最大待机电流:0.000005 A
子类别:Other Microprocessor ICs标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1 mm
端子位置:QUAD紫外线可擦:N
Base Number Matches:1

ZPSD301V-20J 数据手册

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PSD3XX Family  
3.0  
Key Features  
Single-chip programmable peripheral for microcontroller-based applications  
256K to 1 Mbit of UV EPROM with the following features:  
Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16  
Divided into eight equally-sized mappable blocks for optimized address mapping  
As fast as 70 ns access time, which includes address decoding  
Optional 16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be  
as quick as 70 ns, including address decoding.  
19 I/O pins that can be individually configured for :  
Microcontroller I/O port expansion  
Programmable Address decoder (PAD) I/O  
Latched address output  
Open-drain or CMOS output  
Two Programmable Arrays (PAD A and PAD B) replace your PLD or decoder, and have  
the following features:  
Up to 18 Inputs and 24 outputs  
40 Product terms (13 for PAD A and 27 for PAD B)  
Ability to decode up to 1 MB of address without paging  
Microcontroller logic that eliminates the need for external “glue logic” has the following  
features:  
Ability to interface to multiplexed and non-multiplexed buses  
Built-in address latches for multiplexed address/data bus  
ALE and Reset polarity are programmable (Reset polarity not programmable on  
V-versions)  
Multiple configurations are possible for interface to many different microcontrollers  
Optional built-in page logic expands the MCU address space by up to 16 times  
Programmable power management with standby current as low as 1µA for low-voltage  
version  
CMiser bitprogrammable option to reduce AC power consumption in memory  
Turbo Bit (ZPSD only)—programmable bit to reduce AC and DC power consumption  
in the PADs.  
Track Mode that allows other microcontrollers or host processors to share access to the  
local data bus  
Built-in security locks the device and PAD decoding configuration  
Wide Operating Voltage Range  
V-versions: 2.7 to 5.5 volts  
Others: 4.5 to 5.5 volts  
Available in a variety of packaging (44-pin PLDCC, CLDCC, TQFP, and PQFP)  
Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.  
4

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