XR71211
Pin Configuration
1
2
3
4
5
PGOOD
EN
10 AGND
ADJ
9
XR71211
DFN-10
VIN
VOUT
VOUT
PGND
8
VIN
7
6
Thermal Pad
PGND
Pin Assignments
Pin No.
Pin Name
Type
Description
1
PGOOD
EN
OD
Power Good open-drain output. When used it should be pulled up to VIN with a resistor. Typi-
cal resistor value is 100kΩ.
2
I
Enable Input Pin. This is a high impedance MOS input with CMOS logic level compatibility.
Logic high enables the device; logic low disables the device. EN must be asserted high after
VIN reaches its minimum operating range. For automatic startup EN must be sequenced with
respect to VIN as shown in application circuit. Do not pull this pin higher than VIN + 0.5V.
3, 4
VIN
PWR
Power Input Pin. Must be closely decoupled to PGND pin with a 4.7μF or greater ceramic
capacitor.
5, 6
7, 8
PGND
VOUT
PWR
O
Power Ground
Regulator Output pin. Must be closely decoupled to PGND with a 4.7μF or greater ceramic
capacitor.
9
ADJ
I
Adjustable Pin. Connect to a resistive voltage divider to set the output voltage of the device.
Signal ground. Connect with a separate trace to the ground of the output being regulated.
Connect to PGND.
10
AGND
PWR
PWR
Thermal Pad
Type: I = Input, O = Output, I/O = Input/Output, PWR = Power, OD = Open-Drain
4 / 12
exar.com/XR71211
Rev 1B
© 2014 Exar Corporation