XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 27
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 29
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 29
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 30
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 32
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 32
TABLE 12: REGISTER AT ADDRESS OFFSET 0X7 ............................................................................................................................. 33
TABLE 13: REGISTER AT ADDRESS OFFSET 0X6 ............................................................................................................................. 33
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 34
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 34
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 36
4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1)..................... 36
4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ...................................... 36
4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................ 36
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 36
4.14 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 37
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37
4.14.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 38
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39
5.0 ELECTRICAL CHARACTERISTICS...................................................................................................... 40
ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%).............................................. 40
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 41
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 42
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 43
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING................................................................................................................... 43
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 44
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 45
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 45
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 46
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 47
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 47
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 48
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................................................... 49
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)................................................................................ 50
PACKAGE DIMENSIONS (49 PIN SHRINK THIN BALL GRID ARRAY - 4 X 4mm) ................................................. 51
REVISION HISTORY...................................................................................................................................... 52
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