XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.1
JULY 2018
FEATURES
GENERAL DESCRIPTION
1.62 to 3.6 Volt Operation
Selectable I2C/SPI Interface
1
The XR20M1172 is a high performance two channel
universal asynchronous receiver and transmitter
(UART) with 64 byte TX and RX FIFOs and a
SPI clock frequency up to
selectable I2C/SPI slave interface. The XR20M1172
operates from 1.62 to 3.63 volts. The standard
features include 16 selectable TX and RX FIFO
trigger levels, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem interface. Onboard registers provide the user
with operational status and data error flags. An
■ 18 MHz at 3.3 V
■ 16 MHz at 2.5 V
■ 8 MHz at 1.8 V
Full-featured UART
■ Data rate of up to 16 Mbps at 3.3 V
internal
loopback
capability
allows
system
■ Data rate of up to 12.5 Mbps at 2.5 V
■ Data rate of up to 8 Mbps at 1.8 V
diagnostics. Additional enhanced features includes a
programmable fractional baud rate generator and 8X
and 4X sampling rate that allows for a maximum baud
rate of 16 Mbps at 3.3V. The XR20M1172 is available
in the 32-pin QFN and 28-pin TSSOP packages. The
32-pin QFN package has the EN485# and ENIR#
pins to allow the UART to power-up in the Auto
RS485 mode or the Infrared mode.
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 64 bytes
■ 16 Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Halt and Resume Transmission Control
NOTE: 1 Covered by U.S. Patent #5,649,122
■ Automatic RS-485 Half-duplex Direction
APPLICATIONS
Control Output via RTS#
Portable Appliances
■ Wireless Infrared (IrDA 1.0 and 1.1) Encoder/
Decoder
Battery-Operated Devices
Cellular Data Devices
■ Automatic sleep mode (< 30 uA at 3.3V)
■ General Purpose I/Os
Factory Automation and Process Controls
■ Full modem interface
Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
32-QFN and 28-TSSOP packages
FIGURE 1. XR20M1172 BLOCK DIAGRAM
V C C
1 . 6 2 V – 3 . 6 3 V
C h a n n e l 1
T X A
R X A
6 4 B y te
T X F IF O
E N IR #
E N 4 8 5 #
IR Q #
U A R T
R e g s
R T S A #
C T S A #
6 4 B y te
R X F IF O
R E S E T #
S D A
B R G
I2 C / S P I
In te rfa c e
S C K
A 0 / C S #
A 1 / S I
S O
[
]
G P IO 7:0
G P IO s
T X B
R X B
U A R T C h a n n e l 2
(S im ila r to C h a n n e l1 )
R T S B #
C T S B #
C ry s ta l
O s c
B u ffe r
#
I2 C / S P I
/
1