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XLMG3526R030RQST

更新时间： 2023-09-03 20:32:10
品牌 Logo 应用领域
德州仪器 - TI 驱动驱动器
页数 文件大小 规格书
52页 3336K
描述
具有集成驱动器、保护和零电压检测功能的 650V 30mΩ GaN FET | RQS | 52 | -40 to 125

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XLMG3526R030RQST 数据手册

 浏览型号XLMG3526R030RQST的Datasheet PDF文件第1页浏览型号XLMG3526R030RQST的Datasheet PDF文件第2页浏览型号XLMG3526R030RQST的Datasheet PDF文件第4页浏览型号XLMG3526R030RQST的Datasheet PDF文件第5页浏览型号XLMG3526R030RQST的Datasheet PDF文件第6页浏览型号XLMG3526R030RQST的Datasheet PDF文件第7页 
LMG3526R030  
ZHCSRV6A –MARCH 2023 –REVISED APRIL 2023  
www.ti.com.cn  
5 Pin Configuration and Functions  
DRAIN  
16  
15 14  
13 12 11 10  
9
8
7
6
5
4
3
2
1
NC2  
17  
52  
NC2  
18  
19  
20  
21  
22  
23  
24  
25  
26  
51  
50  
49  
48  
47  
46  
45  
44  
43  
LDO5V  
RDRV  
TEMP  
ZVD  
NC2  
FAULT  
IN  
THERMAL PAD  
VDD  
NC2  
27  
28 29  
30 31 32 33 34 35 36 37  
38 39 40 41  
42  
SOURCE  
VNEG  
图5-1. RQS Package, 52-Pin VQFN (Top View)  
表5-1. Pin Functions  
PIN  
TYPE(1)  
DESCRIPTION  
NAME  
NC1  
NO.  
1, 16  
2–15  
Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are  
non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally  
connected to DRAIN.  
—
DRAIN  
NC2  
P
GaN FET drain. Internally connected to NC1.  
Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are  
non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally  
connected to SOURCE, and THERMAL PAD.  
17, 27, 43, 47,  
52  
—
SOURCE  
VNEG  
P
P
GaN FET source. Internally connected to NC2, and THERMAL PAD.  
18–26, 28–39  
Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN  
FET. Bypass to SOURCE with a 2.2-µF capacitor.  
40, 41  
BBSW  
VDD  
IN  
42  
44  
45  
46  
P
P
I
Internal buck-boost converter switch pin. Connect an inductor from this point to SOURCE.  
Device input supply.  
CMOS-compatible non-inverting input used to turn the FET on and off.  
Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.  
FAULT  
O
Push-pull digital output that provides zero-voltage detection signal to indicate if device achieves zero-voltage  
switching in current switching cycle. Refer to 节8.3.11 for details.  
ZVD  
TEMP  
RDRV  
LDO5V  
48  
49  
50  
51  
O
O
I
Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed  
waveform. The device temperature is encoded as the duty cycle of the waveform.  
Drive-strength selection pin. Connect a resistor from this pin to SOURCE to set the turn-on drive strength to  
control slew rate. Tie the pin to SOURCE to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.  
5-V LDO output for external digital isolator. If using this externally, connect a 0.1-µF or greater capacitor to  
SOURCE.  
P
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
3
Product Folder Links: LMG3526R030  
English Data Sheet: SNOSDG2  
 
 
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