XIO3130
SLLS693C–MAY 2007–REVISED JUNE 2008
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4.2.75 Global Switch Control Register ................................................................................ 79
4.2.76 Advanced Error Reporting Capability ID Register........................................................... 80
4.2.77 Next Capability Offset/Capability Version Register ......................................................... 80
4.2.78 Uncorrectable Error Status Register .......................................................................... 80
4.2.79 Uncorrectable Error Mask Register ........................................................................... 81
4.2.80 Uncorrectable Error Severity Register ........................................................................ 82
4.2.81 Correctable Error Status Register............................................................................. 83
4.2.82 Correctable Error Mask Register .............................................................................. 84
4.2.83 Advanced Error Capabilities and Control Register.......................................................... 85
4.2.84 Header Log Register ............................................................................................ 85
PCI Express Downstream Port Registers............................................................................... 86
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
PCI Configuration Space (Downstream Port) Register Map............................................... 86
Vendor ID Register.............................................................................................. 87
Device ID Register .............................................................................................. 87
Command Register.............................................................................................. 87
Status Register .................................................................................................. 88
Class Code and Revision ID Register ........................................................................ 89
Cache Line Size Register ...................................................................................... 90
Primary Latency Timer Register............................................................................... 90
Header Type Register .......................................................................................... 90
4.3.10 BIST Register .................................................................................................... 90
4.3.11 Primary Bus Number............................................................................................ 91
4.3.12 Secondary Bus Number ........................................................................................ 91
4.3.13 Subordinate Bus Number....................................................................................... 91
4.3.14 Secondary Latency Timer Register ........................................................................... 91
4.3.15 I/O Base Register................................................................................................ 92
4.3.16 I/O Limit Register ................................................................................................ 92
4.3.17 Secondary Status Register..................................................................................... 92
4.3.18 Memory Base Register ......................................................................................... 93
4.3.19 Memory Limit Register.......................................................................................... 94
4.3.20 Pre-fetchable Memory Base Register......................................................................... 94
4.3.21 Pre-fetchable Memory Limit Register ......................................................................... 94
4.3.22 Pre-fetchable Base Upper 32 Bits Register.................................................................. 95
4.3.23 Pre-fetchable Limit Upper 32 Bits Register .................................................................. 95
4.3.24 I/O Base Upper 16 Bits Register .............................................................................. 96
4.3.25 I/O Limit Upper 16 Bits Register............................................................................... 96
4.3.26 Capabilities Pointer Register................................................................................... 96
4.3.27 Interrupt Line Register .......................................................................................... 97
4.3.28 Interrupt Pin Register ........................................................................................... 97
4.3.29 Bridge Control Register......................................................................................... 97
4.3.30 Capability ID Register........................................................................................... 99
4.3.31 Next-Item Pointer Register ..................................................................................... 99
4.3.32 Power Management Capabilities Register ................................................................... 99
4.3.33 Power Management Control/Status Register............................................................... 100
4.3.34 Power Management Bridge Support Extension Register................................................. 101
4.3.35 Power Management Data Register.......................................................................... 101
4.3.36 MSI Capability ID Register.................................................................................... 101
4.3.37 Next-Item Pointer Register.................................................................................... 101
4.3.38 MSI Message Control Register............................................................................... 102
4.3.39 MSI Message Address Register ............................................................................. 102
4.3.40 MSI Message Upper Address Register ..................................................................... 103
4.3.41 MSI Message Data Register.................................................................................. 103
4.3.42 Capability ID Register ......................................................................................... 103
4
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