R
Virtex-5 Family Overview
Digitally Controlled Impedance (DCI)
Active I/O Termination
System Monitor
•
•
•
On-Chip temperature measurement ( 4°C)
On-Chip power supply measurement ( 1%)
Easy to use, self-contained
•
•
•
Optional series or parallel termination
Temperature and voltage compensation
Makes board layout much easier
−
−
−
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip
sensors
−
−
Reduces resistors
Places termination in the ideal location, at the signal
source or destination
•
•
User accessible 10-bit 200kSPS ADC
Configuration
−
−
Automatic calibration of offset and gain error
DNL = 0.9 LSBs maximum
•
•
•
Support for platform Flash, standard SPI Flash, or
standard parallel NOR Flash configuration
Bitstream support with dedicated fallback
reconfiguration logic
256-bit AES bitstream decryption provides intellectual
property security and prevents design copying
Improved bitstream error detection/correction capability
Auto bus width detection capability
Up to 17 external analog input channels supported
−
−
−
0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs
•
•
Full access from fabric or JTAG TAP to System Monitor
Fully operational prior to FPGA configuration and
during device power down (access via JTAG TAP only)
•
•
•
Partial Reconfiguration via ICAP port
65-nm Copper CMOS Process
Advanced Flip-Chip Packaging
•
•
1.0V Core Voltage
•
Pre-engineered packaging technology for proven
superior signal integrity
12-layer metal provides maximum routing capability
and accommodates hard-IP immersion
Triple-oxide technology for proven reduced static power
consumption
−
−
Minimized inductive loops from signal to return
Optimal signal-to-PWR/GND ratios
•
•
•
Reduces SSO induced noise by up to 7x
Pb-Free and standard packages
System Blocks Specific to the LXT, SXT, TXT, and FXT Devices
Integrated Endpoint Block for PCI Express
Compliance
Tri-Mode Ethernet Media Access Controller
•
•
•
•
•
Designed to the IEEE 802.3-2002 specification
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-negotiation
Receive address filter (5 address entries)
Fully monolithic 1000Base-X solution with RocketIO
GTP transceivers
•
Works in conjunction with RocketIO GTP transceivers
(LXT and SXT) and GTX transceivers (TXT and FXT)
to deliver full PCI Express Endpoint functionality with
minimal FPGA logic utilization.
•
•
Compliant with the PCI Express Base Specification 1.1
PCI Express Endpoint block or Legacy PCI Express
Endpoint block
•
Supports multiple external PHY connections (RGMII,
GMII, etc.) interfaces through soft logic and SelectIO
resources
•
•
•
•
•
x8, x4, or x1 lane width
Power management support
Block RAMs used for buffering
Fully buffered transmit and receive
Management interface to access PCI Express
configuration space and internal configuration
Supports the full range of maximum payload sizes
Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of
32 bit and 64 bit)
•
•
Supports connection to external PHY device through
SGMII using soft logic and RocketIO GTP transceivers
Receive and transmit statistics available through
separate interface
•
•
•
•
•
Separate host and client interfaces
Support for jumbo frames
Support for VLAN
Flexible, user-configurable host interface
Supports IEEE 802.3ah-2004 unidirectional mode
•
•
4
www.xilinx.com
DS100 (v5.1) August 21, 2015
Product Specification
5秒后页面跳转
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
PCF8574资料解读：主要参数分析、引脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
