Virtex-4 User Guide
0
R
Virtex-4 Family Overview
0
0
DS112 (v1.1) September 10, 2004
Advance Product Specification
General Description
The Virtex-4™ Family is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or
ASMBL™ column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families
(platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of
hard-IP core blocks complete the system solution. These cores include the PowerPC™ processors (with a new APU
interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II,
Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. Virtex-4 devices are produced on a
state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible
features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC
technology.
Summary of Virtex-4 Features
•
Three families LX/SX/FX
•
SelectIO Technology
-
-
Virtex-4 LX: High-performance logic applications solution
Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
Virtex-4 SX: High-performance solution for Digital Signal
Processing (DSP) applications
-
-
-
-
1.5 to 3.3 V I/O Operation
Built-In ChipSync™ Source-Synchronous Technology
Digitally-controlled impedance (DCI) active termination
Fine grained I/O banking (Configuration in one bank)
-
•
•
•
•
•
•
•
•
Flexible Logic Resources
•
•
•
Xesium™ Clock Technology
Built-in System Monitor (voltage/temp. measurement)
10-bit, 200kSPS A/D Converter (ADC)
Secure Chip AES Bitstream Encryption
90-nm copper CMOS process
1.2V core voltage
Flip-Chip Packaging
RocketIO™ 622 Mb/s to 11.1 Gb/s Multi-Gigabit
Transceivers (MGT) (FX only)
-
-
-
Digital Clock Manager (DCM) blocks
Additional Phase-Matched Clock Dividers (PMCD)
Differential Global Clocks
XtremeDSP™ Slice
-
-
-
18x18, two’s complement, signed Multiplier
Optional pipeline stages
Built-In Accumulator (48-bits) & Adder/Subtracter
Smart RAM Memory Hierarchy
-
Distributed RAM
-
Dual-Port 18-Kbit RAM blocks
•
•
IBM PowerPC RISC Processor Core (FX only)
·
·
Optional pipeline stages
Optional programmable FIFO logic - Automatically
remaps RAM signals as FIFO signals
-
PowerPC 405 (PPC405) Core
-
Auxiliary Processor Unit Interface (User Coprocessor)
Multiple Tri-Mode Ethernet MACs (FX only)
-
High-speed memory interface support: DDR and DDR-2
SDRAM, QDR-II, RLDRAM-II, and FCRAM-II
Table 1: Virtex-4 FPGA Family Members
(1)
Configurable Logic Blocks (CLBs)
Block RAM
Xtreme
DSP
Slices
PowerPC
Processor
Blocks
RocketIO Total Max
Transciever I/O User
System ADC
Monitors Blocks
Ethernet
MACs
Array
Row x Col
Logic
Cells
Slices
Max
Distributed
RAM (Kb)
18 Kb
Blocks
Max
Block
RAM (Kb)
Device
DCMs PMCDs
(2)
Blocks
Banks I/O
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
64 x 24
96 x 28
13,824
24,192
41,472
59,904
80,640
6,144
10,752
18,432
26,624
35,840
96
168
288
416
560
768
1056
1392
32
48
64
64
80
96
96
96
48
72
864
4
8
0
4
4
4
8
8
8
8
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
9
320
448
640
640
768
960
960
960
1,296
1,728
2,880
3,600
4,320
5,184
6,048
11
13
13
15
17
17
17
128 x 36
128 x 52
160 x 56
96
8
160
200
240
288
336
8
12
12
12
12
XC4VLX100 192 x 64 110,592 49,152
XC4VLX160 192 x 88 152,064 67,584
XC4VLX200 192 x 116 200,448 89,088
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS112 (v1.1) September 10, 2004
www.xilinx.com
21
Advance Product Specification
5秒后页面跳转
SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
AT89C51单片机资料手册详细解析及应用示例
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
