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XAPP876

更新时间： 2024-09-23 07:56:39

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
26页	1161K
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Virtex-5 FPGA Interface to a JESD204A Compliant ADC

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XAPP876 数据手册

Application Note: Virtex-5 Family

Virtex-5 FPGA Interface to a JESD204A

Compliant ADC

Author: Marc Defossez

XAPP876 (v1.0.1) February 22, 2010

Summary

This application note describes how to interface the Virtex®-5 LXT, SXT, TXT, and FXT devices

featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC

Standard No. 204A (JESD204A) Serial Interface for Data Converters [Ref 1]. With some

restrictions that are highlighted in the text, this application note can also be used for ADC

devices compliant to the older JESD204 standard.

Introduction

The JESD204A standard describes a serialized interface between data converters and logic

devices. It contains normative information to enable the implementation of designs that

communicate with devices covered by the JESD204A standard. This application note

discusses the implementation of a two-lane dual ADC with each lane having a 14-bit resolution

and running at 125 MSPS. It provides an overview of how to implement the serial data interface

and the link protocol described in the JESD204A standard. Although some implementation

modes are discussed in this application note, not all possible implementation modes are

provided in the accompanying reference design.

The JESD204A standard describes the protocol for implementation with general high-speed

SERDES devices. The Virtex-5 TXT device contains GTX transceivers. The JESD204A

standard is interpreted accordingly, and a compliant interface is delivered for GTX transceivers.

Figure 1 shows a comparison between the JESD204A standard and the older JESD204

standard. The implementation described in this application note is for a single device containing

two converters (M), using one link of two lanes (L) connected to the FPGA. For completeness,

the FPGA is always assumed to be a single device.

X-Ref Target - Figure 1

JESD204

JESD204A

One multipoint link.

All lanes aligned.

Similar

Converters

1 Link,

L Lanes

Converters

Logic

Device

(FPGA or

ASIC)

Logic

Device

(FPGA or

ASIC)

1 Lane,

1 Link

Converters

1 Link,

L Lanes

X876_01_072309

Figure 1: Comparison of JESD204 and JESD204A Standards

countries. All other trademarks are the property of their respective owners.

XAPP876 (v1.0.1) February 22, 2010

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