Datasheet > X9269

X9269

更新时间： 2022-12-12 01:39:38

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
24页	366K
描述
Single Supply/Low Power/256-Tap/2-Wire Bus

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X9269 数据手册

X9269

PIN DESCRIPTIONS

Potentiometer Pins

R , R

Bus Interface Pins

The R and R pins are equivalent to the terminal

SERIAL DATA INPUT/OUTPUT (SDA)

connections on a mechanical potentiometer. Since

there are 2 potentiometers, there are 2 sets of R and

The SDA is a bidirectional serial data input/output pin

for a 2-Wire slave device and is used to transfer data

into and out of the device. It receives device address,

opcode, wiper register address and data sent from an

2-Wire master at the rising edge of the serial clock

SCL, and it shifts out data after each falling edge of the

serial clock SCL.

R such that R and R are the terminals of POT 0

and so on.

The wiper pin are equivalent to the wiper terminal of a

mechanical potentiometer. Since there are

potentiometers, there are 2 sets of R such that R

is the terminal of POT 0 and so on.

It is an open drain output and may be wire-ORed with

any number of open drain or open collector outputs.

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the

guidelines for calculating typical values on the bus

pull-up resistors graph.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY

GROUND (V

)

SERIAL CLOCK (SCL)

The V

pin is the system ground.

pin is the system supply voltage. The V

This input is used by 2-Wire master to supply 2-Wire

serial clock to the X9269.

Other Pins

DEVICE ADDRESS (A3 - A0)

NO CONNECT

The address inputs are used to set the least significant

4 bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

Address input in order to initiate communication with

the X9269. A maximum of 16 devices may occupy the

2-Wire serial bus.

No connect pins should be left open. This pins are

used for Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP pin when LOW prevents nonvolatile writes to

the Data Registers.

FN8173.1

March 28, 2005

1 2 345 6 7...24

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