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X9241A

更新时间： 2024-10-04 14:57:11
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页数 文件大小 规格书
17页 717K
描述
Quad Digital Controlled Potentiometers (XDCP?), Non-Volatile/Low Power/2-Wire/64 Taps

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X9241A 数据手册

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DATASHEET  
X9241A  
FN8164  
Rev 7.00  
August 17, 2015  
Quad Digital Controlled Potentionmeters (XDCP™) Non-Volatile/Low  
Power/2-Wire/64 Taps  
The X9241A integrates four digitally controlled  
potentiometers (XDCP) on a monolithic CMOS integrated  
microcircuit.  
Features  
• Four potentiometers in one package  
• 2-wire serial interface  
The digitally controlled potentiometer is implemented using  
63 resistive elements in a series array. Between each  
element are tap points connected to the wiper terminal  
through switches. The position of the wiper on the array is  
controlled by the user through the 2-wire bus interface. Each  
potentiometer has associated with it a volatile Wiper Counter  
Register (WCR) and 4 nonvolatile Data Registers  
(DR0:DR3) that can be directly written to and read by the  
user. The contents of the WCR controls the position of the  
wiper on the resistor array through the switches. Power up  
recalls the contents of DR0 to the WCR.  
• Register oriented format  
- Direct read/write/transfer of wiper positions  
- Store as many as four positions per potentiometer  
• Terminal Voltages: +5V, -3.0V  
• Cascade resistor arrays  
• Low power CMOS  
• High Reliability  
- Endurance–100,000 data changes per bit per register  
- Register data retention–100 years  
The XDCP can be used as a three-terminal potentiometer or  
as a two-terminal variable resistor in a wide variety of  
applications including control, parameter adjustments, and  
signal processing.  
• 16-bytes of nonvolatile memory  
• 3 resistor array values  
- 2k10k50kor combination  
- Cascadable for values of 4kto 200k  
• Resolution: 64 taps each pot  
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC  
packages  
• Pb-free available (RoHS compliant)  
Block Diagram  
V
V
CC  
SS  
V
R
/
H2  
R0  
R2  
V
V
/R  
R0  
R2  
R1  
R3  
R1  
R3  
H0 H0  
WIPER  
COUNTER  
REGISTER  
H2  
WIPER  
COUNTER  
REGISTER  
(WCR)  
REGISTER  
ARRAY  
POT 2  
(WCR)  
/R  
V
V
/R  
L2 L2  
L0 L0  
/R  
V
/R  
W2 W2  
W0 W0  
SCL  
SDA  
INTERFACE  
AND  
CONTROL  
CIRCUITRY  
A0  
A1  
A2  
A3  
8
DATA  
V
/R  
H1 H1  
V
/R  
H3 H3  
R0  
R2  
R1  
R3  
R0  
R2  
R1  
R3  
WIPER  
COUNTER  
REGISTER  
(WCR)  
WIPER  
COUNTER  
REGISTER  
(WCR)  
REGISTER  
ARRAY  
POT 3  
REGISTER  
ARRAY  
POT 1  
V
V
/R  
L1 L1  
V
V
/R  
L3 L3  
/R  
W1 W1  
/R  
W3 W3  
FN8164 Rev 7.00  
August 17, 2015  
Page 1 of 17  
1234567...17

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