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X5083PIZ-2.7 PDF预览

X5083PIZ-2.7

更新时间： 2024-01-29 10:40:50
品牌 Logo 应用领域
英特矽尔 - INTERSIL 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
21页 320K
描述
CPU Supervisor with 8Kbit SPI EEPROM

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X5083PIZ-2.7 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：PDIP, SOIC, TSSOP包装说明：DIP,
针数：8, 8, 8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.66其他特性：RESET THRESHOLD VOLTAGE IS 2.93V
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDIP-T8JESD-609代码：e3
长度：9.525 mm信道数量：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT APPLICABLE认证状态：Not Qualified
座面最大高度：5.334 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：5 V
表面贴装：NO温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE宽度：7.62 mm
Base Number Matches：1

X5083PIZ-2.7 数据手册

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X5083  
®
Data Sheet  
June 15, 2006  
FN8127.3  
CPU Supervisor with 8Kbit SPI EEPROM  
Features  
This device combines four popular functions, Power-on Reset  
Control, Watchdog Timer, Supply Voltage Supervision, and  
Block Lock Serial EEPROM Memory in one package. This  
combination lowers system cost, reduces board space  
requirements, and increases reliability.  
• Low VCC detection and reset assertion  
- Four standard reset threshold voltages  
4.63V, 4.38V, 2.93V, 2.63V  
- Re-program low VCC reset threshold voltage using  
special programming sequence  
- Reset signal valid to VCC = 1V  
Applying power to the device activates the power-on reset  
circuit which holds RESET active for a period of time. This  
allows the power supply and oscillator to stabilize before the  
processor can execute code.  
• Selectable time out watchdog timer  
• Long battery life with low power consumption  
- <50µA max standby current, watchdog on  
- <1µA max standby current, watchdog off  
- <400µA max active current during read  
The Watchdog Timer provides an independent protection  
mechanism for microcontrollers. When the microcontroller fails to  
restart a timer within a selectable time out interval, the device  
activates the RESET signal. The user selects the interval  
from three preset values. Once selected, the interval does  
not change, even after cycling the power.  
• 8Kbits of EEPROM  
• Save critical data with Block Lock™ memory  
- Block lock first or last page, any 1/4 or lower 1/2 of  
EEPROM array  
The device’s low VCC detection circuitry protects the user’s  
system from low voltage conditions, resetting the system  
when VCC falls below the minimum VCC trip point. RESET is  
asserted until VCC returns to the proper operating level and  
stabilizes. Five industry standard VTRIP thresholds are  
available, however, Intersil’s unique circuits allow the threshold  
to be reprogrammed to meet custom requirements or to fine-  
tune the threshold for applications requiring higher precision.  
• Built-in inadvertent write protection  
- Write enable latch  
- Write protect pin  
• SPI Interface - 3.3MHz clock rate  
• Minimize programming time  
- 16 byte page write mode  
- 5ms write cycle time (typical)  
Pinouts  
• SPI modes (0,0 & 1,1)  
8 LD TSSOP  
• Available packages  
RESET  
SCK  
SI  
1
2
3
4
8
7
6
5
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
V
CC  
X5083  
CS/WDI  
SO  
V
• Pb-free plus anneal available (RoHS compliant)  
SS  
WP  
Applications  
• Communications Equipment  
- Routers, Hubs, Switches  
- Set Top Boxes  
8 LD SOIC, 8 LD PDIP  
V
1
2
3
4
8
7
6
5
CS/WDI  
SO  
CC  
• Industrial Systems  
- Process Control  
RESET  
SCK  
SI  
X5083  
WP  
V
SS  
- Intelligent Instrumentation  
• Computer Systems  
- Desktop Computers  
- Network Servers  
• Battery Powered Equipment  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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