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X5083S8-1.8 PDF预览

X5083S8-1.8

更新时间： 2024-01-18 20:59:33
品牌 Logo 应用领域
其他 - ETC 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
20页 140K
描述
SPI Serial EEPROM with Supervisory Features

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中文翻译

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X5083S8-1.8 数据手册

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Replaces X25383  
X5083  
CPU Supervisor with 8Kbit SPI EEPROM  
DESCRIPTION  
FEATURES  
• Selectable time out watchdog timer  
• Low V detection and reset assertion  
This device combines four popular functions, Power-on  
Reset Control, Watchdog Timer, Supply Voltage Super-  
vision, and Block Lock Serial EEPROM Memory in one  
package. This combination lowers system cost, reduces  
board space requirements, and increases reliability.  
CC  
—Five standard reset threshold voltages  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence.  
—Reset signal valid to V = 1V  
CC  
Applying power to the device activates the power on  
reset circuit which holds RESET active for a period of  
time. This allows the power supply and oscillator to  
stabilize before the processor can execute code.  
• Long battery life with low power consumption  
—<50µA max standby current, watchdog on  
—<1µA max standby current, watchdog off  
—<400µA max active current during read  
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V power  
supply versions  
• 8Kbits of EEPROM—1m write cycle endurance  
• Save critical data with Block Lock™ memory  
—Block lock first or last page, any 1/4 or lower 1/2  
of EEPROM array  
• Built-in inadvertent write protection  
—Write enable latch  
—Write protect pin  
• 3.3MHz clock rate  
• Minimize programming time  
—16 byte page write mode  
The Watchdog Timer provides an independent protection  
mechanism for microcontrollers. When the microcontroller  
fails to restart a timer within a selectable time out interval,  
the device activates the RESET signal. The user selects  
the interval from three preset values. Once selected, the  
interval does not change, even after cycling the power.  
The device’s low V  
detection circuitry protects the  
CC  
user’s system from low voltage conditions, resetting  
the system when V falls below the minimum V  
CC  
CC  
trip point. RESET is asserted until V  
returns to the  
CC  
proper operating level and stabilizes. Five industry  
standard V thresholds are available, however, Xicor’s  
TRIP  
—Self-timed write cycle  
—5ms write cycle time (typical)  
• SPI modes (0,0 & 1,1)  
unique circuits allow the threshold to be reprogrammed  
to meet custom requirements or to fine-tune the thresh-  
old for applications requiring higher precision.  
• Available packages  
—8-lead TSSOP, 8-lead SOIC  
BLOCK DIAGRAM  
Watchdog Transition  
Detector  
Watchdog  
Timer Reset  
WP  
Protect Logic  
RESET  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
Reset &  
Watchdog  
Timebase  
16 Bytes  
240 Bytes  
SCK  
CS/WDI  
Logic  
256 Bytes  
V
Threshold  
Reset logic  
CC  
256 Bytes  
240 Bytes  
16 Bytes  
Power On and  
Low Voltage  
Reset  
V
+
-
CC  
Generation  
V
TRIP  
Characteristics subject to change without notice. 1 of 20  
REV 1.1 9/25/00  
www.xicor.com  
1234567...20

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