Datasheet > X45620V20I

X45620V20I

更新时间： 2024-01-26 23:31:44

品牌	Logo	应用领域
英特矽尔 - INTERSIL		电池开关光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
20页	369K
描述
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

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X45620V20I 技术参数

生命周期：	Transferred	包装说明：	PLASTIC, TSSOP-20
Reach Compliance Code：	unknown	风险等级：	5.69
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G20	长度：	7.01 mm
信道数量：	2	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	4.4 mm
Base Number Matches：	1

X45620V20I 数据手册

X45620

PIN DESCRIPTION (Continued)

Name

Function

RESET

/MR

Reset Output/Manual Reset Input. This is an Input/Output pin.

RESET Output. This is an active LOW, open drain output which goes active whenever V_CCfalls

below the minimum V_CCsense level. When RESET is active communication to the device is interrupt-

ed. RESET remains active until V_CCrises above the minimum V_CCsense level for t_PURST. RESET

also goes active on power-up and remains active for t_PURSTafter the power supply stabilizes.

MR Input. This is an active LOW debounced input. When MR is active, the RESET pins are assert-

ed. When MR is released, the RESET remains asserted for t_PURST, and then released.

WDO

Watchdog Output. WDO is an active low, open drain output which goes active whenever the

watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.

V_SS

Ground

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open

drain output, requires the use of a pull-up resistor.

12–13

SCL

Serial Clock. The SCL input is used to clock all data into and out of the device.

No internal connections

V_BATT

Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-

mary V_CCvoltage. The V_BATTvoltage typically provides the supply voltage necessary to maintain

the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect V_BATT

to ground.

V_OUT

Output Voltage.

_OUT= V_CCif V_CC> V_TRIP1

IF V_CC< V_TRIP1, then,

V_OUT= V_CCif V_CC> V_BATT+0.03

_OUT= V_BATTif V_CC< V_BATT-0.03

Note: There is hysteresis around V_BATT± 0.03V point to avoid oscillation at or near the

switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.

BATT-ON Battery On. This CMOS output goes HIGH when the V_OUTswitches to V_BATTand goes LOW

when V_OUTswitches to V_CC. It is used to drive a external P-channel FET when V_CC= V_OUTand

current requirements are greater than 50mA.

The purpose of this output is to drive an external FET to get higher operating currents when the

_CCsupply is fully functional. In the event of a V_CCfailure, the battery voltage is applied to the

_OUTpin and the external transistor is turned off. In this “backup condition,” the battery only needs

to supply enough voltage and current to keep SRAM devices from losing their data-there is no

communication at this time.

No Connect

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the Watchdog Timer control and the memory write protect bits. This pin has an internal pull down

resistor. (>10MΩ typical)

V_CC

Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1

voltage, RESET and LOWLINE go ACTIVE.

(V1MON)

FN8250.0

July 29, 2005

1 234 5 6 7...20

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