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X4163S8I PDF预览

X4163S8I

更新时间: 2024-01-12 15:49:53
品牌 Logo 应用领域
英特矽尔 - INTERSIL 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
21页 330K
描述
CPU Supervisor with 16K EEPROM

X4163S8I 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:ROHS COMPLIANT, SOIC-8针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.69
其他特性:RESET THRESHOLD VOLTAGE IS 4.38V可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9022 mm
信道数量:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.7272 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9116 mm
Base Number Matches:1

X4163S8I 数据手册

 浏览型号X4163S8I的Datasheet PDF文件第4页浏览型号X4163S8I的Datasheet PDF文件第5页浏览型号X4163S8I的Datasheet PDF文件第6页浏览型号X4163S8I的Datasheet PDF文件第8页浏览型号X4163S8I的Datasheet PDF文件第9页浏览型号X4163S8I的Datasheet PDF文件第10页 
X4163, X4165  
Writing to the Control Register  
– The RWEL bit cannot be reset without writing to the  
nonvolatile control bits in the control register, power  
cycling the device or attempting a write to a write  
protected block.  
Changing any of the nonvolatile bits of the control reg-  
ister requires the following steps:  
– Write a 02H to the Control Register to set the Write  
Enable Latch (WEL). This is a volatile operation, so  
there is no delay after the write. (Operation pre-  
ceeded by a start and ended with a stop).  
To illustrate, a sequence of writes to the device con-  
sisting of [02H, 06H, 02H] will reset all of the nonvola-  
tile bits in the Control Register to 0. A sequence of  
[02H, 06H, 06H] will leave the nonvolatile bits  
unchanged and the RWEL bit remains set.  
– Write a 06H to the Control Register to set both the  
Register Write Enable Latch (RWEL) and the WEL  
bit. This is also a volatile cycle. The zeros in the data  
byte are required. (Operation preceeded by a start  
and ended with a stop).  
SERIAL INTERFACE  
Serial Interface Conventions  
– Write a value to the Control Register that has all the  
control bits set to the desired state. This can be rep-  
resented as 0xys t01r in binary, where xy are the  
WD bits. (Operation preceeded by a start and ended  
with a stop). Since this is a nonvolatile write cycle it  
will take up to 10ms to complete. The RWEL bit is  
reset by this cycle and the sequence must be  
repeated to change the nonvolatile bits again. If bit 2  
is set to ‘1’ in this third step (0xys t11r) then the  
RWEL bit is set, but the BP2, BP1, BP0, WD1 and  
WD0 bits remain unchanged. Writing a second byte  
to the control register is not allowed. Doing so aborts  
the write operation and returns a NACK.  
The device supports a bidirectional bus oriented proto-  
col. The protocol defines any device that sends data  
onto the bus as a transmitter, and the receiving device  
as the receiver. The device controlling the transfer is  
called the master and the device being controlled is  
called the slave. The master always initiates data  
transfers, and provides the clock for both transmit and  
receive operations. Therefore, the devices in this fam-  
ily operate as slaves in all applications.  
Serial Clock and Data  
Data states on the SDA line can change only during  
SCL LOW. SDA state changes during SCL HIGH are  
reserved for indicating start and stop conditions. See  
Figure 5.  
– A read operation occurring between any of the previ-  
ous operations will not interrupt the register write  
operation.  
Figure 5. Valid Data Changes on the SDA Bus  
SCL  
SDA  
Data Stable  
Data Change  
Data Stable  
FN8120.0  
7
April 13, 2005  

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