Datasheet > X4163S8I-4.5A

X4163S8I-4.5A

更新时间： 2024-01-13 16:19:46

品牌	Logo	应用领域
英特矽尔 - INTERSIL		光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
21页	330K
描述
CPU Supervisor with 16K EEPROM

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技术参数
数据手册

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X4163S8I-4.5A 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	PLASTIC, SOIC-8	Reach Compliance Code：	unknown
风险等级：	5.76	Is Samacsys：	N
可调阈值：	YES	模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	4.89 mm	信道数量：	1
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

X4163S8I-4.5A 数据手册

X4163, X4165

Writing to the Control Register

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

Changing any of the nonvolatile bits of the control reg-

ister requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

To illustrate, a sequence of writes to the device con-

sisting of [02H, 06H, 02H] will reset all of the nonvola-

tile bits in the Control Register to 0. A sequence of

[02H, 06H, 06H] will leave the nonvolatile bits

unchanged and the RWEL bit remains set.

– Write a 06H to the Control Register to set both the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

SERIAL INTERFACE

Serial Interface Conventions

– Write a value to the Control Register that has all the

control bits set to the desired state. This can be rep-

resented as 0xys t01r in binary, where xy are the

WD bits. (Operation preceeded by a start and ended

with a stop). Since this is a nonvolatile write cycle it

will take up to 10ms to complete. The RWEL bit is

reset by this cycle and the sequence must be

repeated to change the nonvolatile bits again. If bit 2

is set to ‘1’ in this third step (0xys t11r) then the

RWEL bit is set, but the BP2, BP1, BP0, WD1 and

WD0 bits remain unchanged. Writing a second byte

to the control register is not allowed. Doing so aborts

the write operation and returns a NACK.

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 5.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

Figure 5. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable

Data Change

Data Stable

FN8120.0

April 13, 2005

1...4 5 678 9 10...21

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与X4163S8I-4.5A相关器件

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X4163S8IZ	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, ROHS COMPLIANT, SOIC-8	获取价格
X4163S8IZ-2.7	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8IZ-2.7A	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8IZ-2.7A	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, ROHS COMPLIANT, SOIC-8	获取价格
X4163S8IZ-4.5A	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8IZ-4.5A	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, ROHS COMPLIANT, SOIC-8	获取价格

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