Datasheet > X4163S8I-2.7A

X4163S8I-2.7A

更新时间： 2024-02-24 02:09:43

品牌	Logo	应用领域
英特矽尔 - INTERSIL		光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
21页	330K
描述
CPU Supervisor with 16K EEPROM

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技术参数
数据手册

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X4163S8I-2.7A 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	PLASTIC, SOIC-8	Reach Compliance Code：	unknown
风险等级：	5.76	Is Samacsys：	N
可调阈值：	YES	模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	4.89 mm	信道数量：	1
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

X4163S8I-2.7A 数据手册

X4163, X4165

Setting the V

Voltage

Resetting the V

Voltage

TRIP

This procedure is used to set the V

to a higher or

This procedure is used to set the V

to a “native”

TRIP

lower voltage value. It is necessary to reset the trip

point before setting the new value.

voltage level. For example, if the current V

is 4.4V

must

TRIP

and the new V

must be 4.0V, then the V

TRIP

be reset. When V

thing less than 1.7V. This procedure must be used to

set the voltage to a lower value.

is reset, the new V

is some-

TRIP

To set the new V

bit in the control register, then apply the desired V

threshold voltage to the V pin and the programming

voltage, start by setting the WEL

TRIP

voltage, V , to the WP pin and 2 byte address and 1

To reset the new V

voltage start by setting the

TRIP

byte of “00” data. The stop bit following a valid write

WEL bit in the control register, apply V and the pro-

operation initiates the V

programming sequence.

gramming voltage, V , to the WP pin and 2 byte

TRIP

Bring WP LOW to complete the operation.

address and 1 byte of “00” data. The stop bit of a valid

write operation initiates the V

programming

TRIP

sequence. Bring WP LOW to complete the operation.

Figure 2. Reset V

Level Sequence (V > 3V. WP = 12–15V, WEL bit set)

TRIP

V_P= 12-15V

0 1 2 3 4 5 6 7

SCL

SDA

A0h

00h

03h

00h

Figure 3. Sample V

Reset Circuit

TRIP

V_P

SOIC

Adjust

4.7K

µC

RESET

Run

X4163

V_TRIP

Adj.

SCL

SDA

FN8120.0

April 13, 2005

1 2 345 6 7...21

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