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X4163S8I-2.7A

更新时间： 2024-02-14 22:24:41
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
22页 924K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8

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X4163S8I-2.7A 技术参数

是否Rohs认证：不符合生命周期：Transferred
包装说明：PLASTIC, SOIC-8Reach Compliance Code：unknown
风险等级：5.76Is Samacsys：N
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.89 mm信道数量：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

X4163S8I-2.7A 数据手册

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X4163, X4165  
PRINCIPLES OF OPERATION  
Power On Reset  
WATCHDOG TIMER  
The Watchdog Timer circuit monitors the microprocessor  
activity by monitoring the SDA and SCL pins. The  
microprocessor must periodically send a start bit followed by a  
stop bit prior to the expiration of the watchdog time out period  
to prevent a RESET/RESET signal. The start and stop bits  
need to be separated by SCL toggling low then high at least  
one time.  
Application of power to the X4163, X4165 activates a  
Power On Reset Circuit that pulls the RESET/RESET  
pin active. This signal provides several benefits.  
It prevents the system microprocessor from starting to operate  
with insufficient voltage.  
The state of two nonvolatile control bits in the Status Register  
determine the watchdog timer period. The microprocessor can  
change these watchdog bits, or they may be “locked” by tying  
the WP pin HIGH.  
It prevents the processor from operating prior to stabilization of  
the oscillator.  
It allows time for an FPGA to download its configuration prior to  
initialization of the circuit.  
EEPROM INADVERTENT WRITE PROTECTION  
It prevents communication to the EEPROM, greatly reducing the  
likelihood of data corruption on power up.  
When RESET/RESET goes active as a result of a low  
voltage condition or Watchdog Timer Time Out, any in-  
progress communications are terminated. While  
RESET/RESET is active, no new communications are  
allowed and no nonvolatile write operation can start.  
Nonvolatile writes in-progress when RESET/RESET  
goes active are allowed to finish.  
When VCC exceeds the device VTRIP threshold value for 200ms  
(nominal) the circuit releases RESET/RESET allowing the  
system to begin operation.  
LOW VOLTAGE MONITORING  
During operation, the X4163, X4165 monitors the VCC level  
and asserts RESET/RESET if supply voltage falls below a  
preset minimum VTRIP. The RESET/RESET signal prevents the  
microprocessor from operating in a power fail or brownout  
condition. The RESET/RESET signal remains active until the  
voltage drops below 1V. It also remains active until VCC returns  
and exceeds VTRIP for 200ms.  
Additional protection mechanisms are provided with  
memory Block Lock and the Write Protect (WP) pin.  
These are discussed elsewhere in this document.  
V
THRESHOLD RESET PROCEDURE  
CC  
The X4163, X4165 is shipped with a standard V  
CC  
threshold (V  
) voltage. This value will not change  
TRIP  
over normal operating and storage conditions. However,  
in applications where the standard V is not exactly  
TRIP  
right, or if higher precision is needed in the V  
value,  
TRIP  
the X4163, X4165 threshold may be adjusted. The pro-  
cedure is described below, and uses the application of a  
nonvolatile control signal.  
Figure 1. Set V  
Level Sequence (V = desired V values WEL bit set)  
TRIP  
TRIP  
CC  
VP = 12-15V  
WP  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
SCL  
SDA  
A0h  
00h  
01h  
00h  
FN8120 Rev 2.00  
November 26, 2007  
Page 5 of 22  
12345678...22

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