Datasheet > X4163S8-2.7AT1

X4163S8-2.7AT1

更新时间： 2024-01-28 05:04:23

品牌	Logo	应用领域
瑞萨 - RENESAS		光电二极管
页数	文件大小	规格书
22页	924K
描述
IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8, Power Management Circuit

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数据手册

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X4163S8-2.7AT1 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP,
针数：	8	Reach Compliance Code：	compliant
风险等级：	5.76	Is Samacsys：	N
其他特性：	RESET THRESHOLD VOLTAGE IS 2.92V	可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.9022 mm
湿度敏感等级：	1	信道数量：	1
功能数量：	1	端子数量：	8
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.7272 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9116 mm	Base Number Matches：	1

X4163S8-2.7AT1 数据手册

X4163, X4165

Figure 4. V

Programming Sequence

TRIP

V_TRIPProgramming

Execute

Reset V_TRIP

Sequence

Set V_CC= V_CCApplied =

Desired V_TRIP

New V_CCApplied =

Old V_CCApplied + Error

New V_CCApplied =

Old V_CCApplied - Error

Execute

Set V_TRIP

Sequence

Execute

Reset V_TRIP

Sequence

Apply 5V to V_CC

Decrement V_CC

(V_CC= V_CC- 50mV)

RESET pin

goes active?

YES

Error –Emax

Error  Emax

Measured V_TRIP

Desired V_TRIP

–Emax < Error < Emax

DONE

Emax = Maximum Allowed V_TRIPError

Control Register

The user must issue a stop after sending this byte to the

and WD0. The X4163, X4165 will not acknowledge any

data bytes written after the first byte is entered.

The Control Register provides the user a mechanism for

changing the Block Lock and Watchdog Timer settings.

The Block Lock and Watchdog Timer bits are nonvolatile

and do not change when power is removed.

The state of the Control Register can be read at any time

by performing a random read at address FFFFh. Only

one byte is read by each register read operation. The

X4163, X4165 resets itself after the first byte is read.

The master should supply a stop condition to be consis-

tent with the bus protocol, but a stop is not required to

end this operation.

The Control Register is accessed at address FFFFh. It

can only be modified by performing a byte write opera-

tion directly to the address of the register and only one

data byte is allowed for each register write operation.

Prior to writing to the Control Register, the WEL and

RWEL bits must be set using a two step process, with

the whole sequence requiring 3 steps. See "Writing to

the Control Register" below.

WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2

FN8120 Rev 2.00

November 26, 2007

Page 7 of 22

1...4 5 678 9 10...22

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与X4163S8-2.7AT1相关器件

型号	品牌	描述	获取价格	数据表
X4163S8-2.7A-T1	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8	获取价格
X4163S8-4.5A	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8-4.5A	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8	获取价格
X4163S8I	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8I	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8	获取价格
X4163S8I-2.7	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格

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