X28C512, X28C513
Pinouts
PLCC/LCC
Plastic DIP
CERDIP
FLAT Pack
SOIC (R)
30
29
4
3
2
32 31
A
A
A
5
A
14
7
6
5
1
A
28
6
7
13
PGA
A
27
26
8
A
A
A
8
9
4
3
9
I/O
15
I/O
17
I/O
I/O
21
I/O
22
0
2
1
3
5
4
6
7
X28C512
(Top View)
NC
NC
V
1
32
A
25
24
23
22
CC
11
19
A
A
10
11
OE
2
1
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
NC
CE
24
A
13
A
I/O
16
V
SS
18
I/O
20
I/O
23
1
0
A
10
14
A
3
A
12
13
CE
I/O
15
0
OE
26
A
A
A
10
25
I/O
2
3
0
7
15 16 17 18 19 20
4
A
A
14
12
21
12
11
14
A
5
A
7
13
A
A
A
A
9
28
4
5
11
Bottom
View
10
9
7
27
A
8
A
6
6
A
A
A
A
13
30
6
7
8
A
5
7
A
9
29
8
A
4
8
A
11
A
NC
V
NC
34
NC
32
X28C512
A
A
14
31
15
CC
12
A
3
OE
6
5
4
2
36
9
30
29
A
2
A
NC
NC
NC
1
NC
33
10
11
12
13
14
15
16
WE
35
10
4
3
2
32 31
A
5
A
8
A
9
6
5
4
3
1
A
1
CE
I/O
A
A
28
6
7
A
27
26
11
A
0
5
A
A
NC
OE
8
9
3
2
X28C513
(Top View)
I/O
I/O
I/O
I/O
I/O
0
25
24
23
22
4
3
2
1
A
A
A
10
11
10
1
0
I/O
1
CE
I/O
I/O
2
NC
I/O
12
13
7
I/O
0
6
15 16 17 18 19 20
V
SS
21
14
Pin Descriptions
Pin Names
Addresses (A0-A15
)
SYMBOL
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
The Address inputs select an 8-bit memory location during a
read or write operation.
A -A
0
15
I/O -I/O
0
7
Chip Enable (CE)
WE
CE
OE
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
V
CC
The Output Enable input controls the data output buffers and
is used to initiate read operations.
V
Ground
SS
NC
No Connect
Data In/Data Out (I/O -I/O )
0
7
Data is written to or read from the X28C512, X28C513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C512, X28C513.
FN8106.2
June 7, 2006
4