Datasheet > X1241V8I-2.7

X1241V8I-2.7

更新时间： 2024-01-18 22:08:57

品牌	Logo	应用领域
瑞萨 - RENESAS		时钟光电二极管外围集成电路
页数	文件大小	规格书
22页	195K
描述
0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, TSSOP-8

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技术参数
数据手册

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X1241V8I-2.7 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	PLASTIC, TSSOP-8	Reach Compliance Code：	unknown
风险等级：	5.75	最大时钟频率：	0.032 MHz
信息访问方法：	I2C	中断能力：	N
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	4.4 mm	端子数量：	8
计时器数量：		最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3/3.3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Timer or RTC
最大供电电压：	3.6 V	最小供电电压：	2.7 V
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
最短时间：	SECONDS	易失性：	YES
宽度：	3 mm	uPs/uCs/外围集成电路类型：	TIMER, REAL TIME CLOCK
Base Number Matches：	1

X1241V8I-2.7 数据手册

X1241 – Preliminary Information

RWEL: Register Write Enable Latch—Volatile

Table 3. Block Protect Bits

Protected Addresses

This bit is a volatile latch that powers up in the LOW

(disabled) state. The RWEL bit must be set to “1” prior

to any writes to the Clock/Control Registers. Writes to

RWEL bit do not cause a nonvolatile write cycle, so the

device is ready for the next operation immediately after

the stop condition. A write to the CCR requires both

the RWEL and WEL bits to be set in a speciﬁc

sequence.

X1241

Array Lock

None

600 - 7FF

Upper 1/4

Upper 1/2

Full Array

First Page

First 2 pgs

First 4 pgs

First 8 pgs

400 - 7FF

000 - 7FF

000 - 03F

WEL: Write Enable Latch—Volatile

000 - 07F

The WEL bit controls the access to the CCR and mem-

ory array during a write operation. This bit is a volatile

latch that powers up in the LOW (disabled) state. While

the WEL bit is LOW, writes to the CCR or any array

address will be ignored (no acknowledge will be issued

after the Data Byte). The WEL bit is set by writing a “1”

to the WEL bit and zeroes to the other bits of the Sta-

tus Register. Once set, WEL remains set until either

reset to 0 (by writing a “0” to the WEL bit and zeroes to

the other bits of the Status Register) or until the part

powers up again. Writes to WEL bit do not cause a non

volatile write cycle, so the device is ready for the next

operation immediately after the stop condition.

000 - 0FF

000 - 1FF

Watchdog Timer Control Bits

The bits WD1 and WD0 control the period of the

Watchdog Timer. See Table 4 options.

Table 4. Watchdog Time Out Options

WD1

WD0

Watchdog Time Out Period

1.75 seconds

750 milliseconds

250 milliseconds

disabled

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a ‘1’ after a total power failure. This is a

read only bit that is set by hardware when the device

powers up after having lost all power to the device. The

WRITING TO THE CLOCK/CONTROL REGISTERS

bit is set regardless of whether V

or V

Changing any of the nonvolatile bits of the clock/control

BACK

applied ﬁrst. The loss of one or the other supplies does

not result in setting the RTCF bit. The ﬁrst valid write to

the RTC (writing one byte is sufﬁcient) resets the

RTCF bit to ‘0’.

– Write a 02H to the Status Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

Unused Bits

– Write a 06H to the Status Register to set both the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

These devices do not use bits 3 through 6, but must have

a zero in these bit positions. The Data Byte output during

a SR read will contain zeros in these bit locations.

CONTROL REGISTERS

– Write one to 8 bytes to the Clock/Control Registers

with the desired clock, or control data. This

Block Protect Bits–BP2, BP1, BP0—Nonvolatile

sequence starts with a start bit, requires a slave byte

of “11011110” and an address within the CCR and is

terminated by a stop bit. A write to the CCR changes

EEPROM values so these initiate a nonvolatile write

cycle and will take up to 10ms to complete. Writes to

undeﬁned areas have no effect. The RWEL bit is

reset by the completion of a nonvolatile write cycle,

so the sequence must be repeated to again initiate

The Block Protect Bits, BP2, BP1 and BP0, determine

which blocks of the array are write protected. A write to

a protected block of memory is ignored. The block pro-

tect bits will prevent write operations to one of eight

segments of the array. The partitions are described in

Table 3.

Characteristics subject to change without notice. 5 of 22

REV 1.1.3 2/13/01

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1 2 3 456 7 8...22

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与X1241V8I-2.7相关器件

型号	品牌	描述	获取价格	数据表
X1241V8I-2.7A	RENESAS	Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8	获取价格
X1241V8I-4.5A	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, TSSOP-8	获取价格
X1242S8	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, SOIC-8	获取价格
X1242S8-2.7	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, SOIC-8	获取价格
X1242S8-2.7A	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, SOIC-8	获取价格
X1242S8-4.5A	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, SOIC-8	获取价格

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