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X1228V14Z-2.7AT1 PDF预览

X1228V14Z-2.7AT1

更新时间: 2024-02-17 05:43:58
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟光电二极管外围集成电路
页数 文件大小 规格书
29页 430K
描述
1 TIMER(S), REAL TIME CLOCK, PDSO14, ROHS COMPLIANT, PLASTIC, TSSOP-14

X1228V14Z-2.7AT1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.62
最大时钟频率:0.032 MHz信息访问方法:I2C
中断能力:YJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:5 mm
端子数量:14计时器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Timer or RTC
最大供电电压:5.5 V最小供电电压:2.7 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
最短时间:SECONDS处于峰值回流温度下的最长时间:NOT SPECIFIED
易失性:YES宽度:4.4 mm
uPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCKBase Number Matches:1

X1228V14Z-2.7AT1 数据手册

 浏览型号X1228V14Z-2.7AT1的Datasheet PDF文件第20页浏览型号X1228V14Z-2.7AT1的Datasheet PDF文件第21页浏览型号X1228V14Z-2.7AT1的Datasheet PDF文件第22页浏览型号X1228V14Z-2.7AT1的Datasheet PDF文件第24页浏览型号X1228V14Z-2.7AT1的Datasheet PDF文件第25页浏览型号X1228V14Z-2.7AT1的Datasheet PDF文件第26页 
X1228  
Random Read  
read from the newly loaded address. This operation  
could be useful if the master knows the next address it  
needs to read, but is not ready for the data.  
Random read operations allows the master to access  
any location in the X1228. Prior to issuing the Slave  
Address Byte with the R/W bit set to zero, the master  
must first perform a “dummy” write operation.  
Sequential Read  
Sequential reads can be initiated as either a current  
address read or random address read. The first data  
byte is transmitted as with the other modes; however,  
the master now responds with an acknowledge, indi-  
cating it requires additional data. The device continues  
to output data for each acknowledge received. The  
master terminates the read operation by not responding  
with an acknowledge and then issuing a stop condition.  
The master issues the start condition and the slave  
address byte, receives an acknowledge, then issues  
the word address bytes. After acknowledging receipt  
of each word address byte, the master immediately  
issues another start condition and the slave address  
byte with the R/W bit set to one. This is followed by an  
acknowledge from the device and then by the eight bit  
data word. The master terminates the read operation  
by not responding with an acknowledge and then issu-  
ing a stop condition. Refer to Figure 16 for the  
address, acknowledge, and data transfer sequence.  
The data output is sequential, with the data from  
address n followed by the data from address n + 1.  
The address counter for read operations increments  
through all page and column addresses, allowing the  
entire memory contents to be serially read during one  
operation. At the end of the address space the counter  
“rolls over” to the start of the address space and the  
X1228 continues to output data for each acknowledge  
received. Refer to Figure 17 for the acknowledge and  
data transfer sequence.  
In a similar operation called “Set Current Address,” the  
device sets the address if a stop is issued instead of  
the second start shown in Figure 16. The X1228 then  
goes into standby mode after the stop and all bus  
activity will be ignored until a start is detected. This  
operation loads the new address into the address  
counter. The next Current Address Read operation will  
Figure 16. Random Address Read Sequence  
S
t
S
S
t
o
p
t
a
r
Signals from  
the Master  
Slave  
Address  
Word  
Address 0  
Slave  
Address  
a
r
Word  
Address 1  
t
t
SDA Bus  
1
1 1 1 1  
1
1 1 1 0  
0 0 0 0 0 0 0  
A
C
K
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Data  
Figure 17. Sequential Read Sequence  
S
t
o
p
Slave  
Address  
A
C
K
A
C
K
A
C
K
Signals from  
the Master  
SDA Bus  
1
A
C
K
Signals from  
the Slave  
Data  
(1)  
Data  
(2)  
Data  
(n-1)  
Data  
(n)  
(n is any integer greater than 1)  
FN8100.2  
23  
October 17, 2005  

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